Abstract: A method of making a semiconductor memory device is discussed, which has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m.

Abstract: A semiconductor memory device has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m. In another method, implantation process are carried out in two steps so as to force the previously implanted ions deeper into the storage node electrode, and a subsequent heat treatment is carried out to further distribute the dopant ions into the substrate of the semiconductor substrate so as to disperse crystal defects into the substrate.