Abstract: In order to solve a problem of achieving distortion compensation with high accuracy, a digital filter device includes a first distortion compensation filter unit for conducting distortion compensation of first waveform distortion included in an inputted signal through digital signal processing, a first filter coefficient setting unit for setting a filter coefficient of the first distortion compensation filter unit, a second distortion compensation filter unit for compensating second waveform distortion included in a signal outputted from the first distortion compensation filter unit, and a second filter coefficient setting unit for setting a filter coefficient of the second distortion compensation filter unit based on the filter coefficient set by the first filter coefficient setting unit.

Abstract: An analog-to-digital converter according to the present invention includes first and second analog-to-digital conversion cells (11, 12), control means (10) for, when a mode specifying signal MD indicates a first mode, generating a control signal that sets first and second input ranges to the same voltage range and sets first and second clocks to different phases, and when the mode specifying signal MD indicates a second mode, generating the control signal that sets the first and second input ranges to one continuous voltage range and sets the first and second clocks to the same phase, ADC cell control means (111) for controlling the voltage ranges of the first and second input ranges according to the control signal, and a sampling clock generation unit (112) that generates the first and second sampling clocks according to the control signal.

Abstract: A digital receiver includes: an analog-to-digital (AD) converter (102) for setting discrimination levels in accordance with a discrimination level control signal and converting an analog input signal into a digital signal based on the set discrimination levels; a discrimination level adjusting circuit (104) for generating the discrimination level control signal and outputting the discrimination level control signal to the AD converter; a signal quality monitoring portion (108) for generating a transfer function correction control signal, which is information about a transfer function of the AD converter; and a transfer function correcting circuit (106) for performing signal processing on the digital signal so as to cancel a gap between the transfer function of the AD converter and an initial transfer function based on the transfer function correction control signal.

Abstract: Each of cascade-connected one-bit A/D converters includes first and second amplifier circuits receiving first and second input signals, a third amplifier circuit that outputs an interpolation value of outputs of the first and second amplifier circuits, a comparator that outputs a binary signal having value determined by a polarity of an output of the third amplifier circuit, and a selector that selects two of three outputs of the first to third amplifier circuits, based on a value of the comparator. The selector is set such that direct-current transfer characteristics of two outputs of the selector are folded and symmetrical relative to the midpoint of the first and second input signals.

Abstract: A time-interleaved A/D converter apparatus has a primary signal A/D converter circuit group that is time-interleaved with a combination of N A/D converter circuits, a correction signal generation part operable to receive the input analog signal and a 1/m-sampling signal having a speed that is 1/m of a rate of the sampling signal inputted to the primary signal A/D converter circuit group, to extract a dispersion of a transmission line that is immanent in the input analog signal, and to output the dispersion as a dispersion compensation control signal used for digital signal compensation, and a signal processing part operable to convert the N digital signals into one digital signal based upon the dispersion compensation control signal and to compensate a dispersion included in the converted digital signal.

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract: A sample and hold circuit comprises an input stage amplifier circuit for amplifying an input signal and a hold circuit for holding an output signal of the input stage amplifier circuit, with a sampling clock signal as a trigger, is further provided with a bias current switching circuit for switching a bias current of the input stage amplifier circuit to another circuit that is functionally independent of the sample and hold circuit, in a case where the hold circuit is in a hold period, to supply the bias current to the circuit.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: In order to solve a problem of achieving distortion compensation with high accuracy, a digital filter device includes a first distortion compensation filter unit for conducting distortion compensation of first waveform distortion included in an inputted signal through digital signal processing, a first filter coefficient setting unit for setting a filter coefficient of the first distortion compensation filter unit, a second distortion compensation filter unit for compensating second waveform distortion included in a signal outputted from the first distortion compensation filter unit, and a second filter coefficient setting unit for setting a filter coefficient of the second distortion compensation filter unit based on the filter coefficient set by the first filter coefficient setting unit.

Abstract: An analog-to-digital conversion device which converts an analog input signal into a digital signal and output it includes a signal characteristic detection unit for detecting a predetermined characteristic of the input signal; a control signal generation unit for setting a resolution based on the signal characteristic detected by the signal characteristic detection unit, generating a control signal that indicates only an operation required for performing the analog-to-digital conversion at the resolution, and outputting it; and an analog-to-digital conversion unit for restricting the operation based on the control signal and converting the input signal into the digital signal at the set resolution.

Abstract: A sample and hold circuit that is provided with an input stage amplifier circuit for amplifying an input signal and a hold circuit for holding an output signal of the input stage amplifier circuit, with a sampling clock signal as a trigger, is further provided with a hold circuit bias current switching circuit for switching a bias current of the hold circuit to a first separate circuit that is functionally independent of the sample and hold circuit, in a case where the hold circuit is in a hold period, to supply the bias current to the circuit.

Abstract: To provide an optical phase modulation circuit and an optical phase modulation method capable of achieving a high-speed operation without increasing the power consumption. An optical phase modulation circuit according to the present invention includes an optical modulation unit 50 that includes a plurality of division electrodes 12 to 15 connected in tandem and generates a modulation signal by summing up optical signals modulated by using respective division electrodes, drive circuits 8 to 11 that drive the plurality of division electrodes, and a modulation timing control unit 60 that controls timings at which the optical signals are modulated in the plurality of division electrodes 12 to 15, by controlling an operation timing of the drive circuits 8 to 11.

Abstract: Provided is an electronic circuit system which facilitates skew timing adjustment while preventing increase of power consumption. An electronic circuit system includes: a track hold circuit module formed by a hierarchical tree structure of track hold circuits which can track-hold an analog value of an analog signal; and a control signal generation module which supplies an operation control signal to each of the track hold circuits in the hierarchical tree structure. In the hierarchical tree structure, the number of track hold circuits of each of the hierarchies is stepwise changed from the first hierarchy of the input side to which an analog signal is inputted, toward the final hierarchy of the final output side as the number of hierarchies is increased.

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract: A time-interleaved A/D converter apparatus has a primary signal A/D converter circuit group that is time-interleaved with a combination of N A/D converter circuits, a correction signal generation part operable to receive the input analog signal and a 1/m-sampling signal having a speed that is 1/m of a rate of the sampling signal inputted to the primary signal A/D converter circuit group, to extract a dispersion of a transmission line that is immanent in the input analog signal, and to output the dispersion as a dispersion compensation control signal used for digital signal compensation, and a signal processing part operable to convert the N digital signals into one digital signal based upon the dispersion compensation control signal and to compensate a dispersion included in the converted digital signal.

Abstract: Each of cascade-connected one-bit A/D converters includes first and second amplifier circuits receiving first and second input signals, a third amplifier circuit that outputs an interpolation value of outputs of the first and second amplifier circuits, a comparator that outputs a binary signal having value determined by a polarity of an output of the third amplifier circuit, and a selector that selects two of three outputs of the first to third amplifier circuits, based on a value of the comparator. The selector is set such that direct-current transfer characteristics of two outputs of the selector are folded and symmetrical relative to the midpoint of the first and second input signals.

Abstract: A digital receiver includes: an analog-to-digital (AD) converter (102) for setting discrimination levels in accordance with a discrimination level control signal and converting an analog input signal into a digital signal based on the set discrimination levels; a discrimination level adjusting circuit (104) for generating the discrimination level control signal and outputting the discrimination level control signal to the AD converter; a signal quality monitoring portion (108) for generating a transfer function correction control signal, which is information about a transfer function of the AD converter; and a transfer function correcting circuit (106) for performing signal processing on the digital signal so as to cancel a gap between the transfer function of the AD converter and an initial transfer function based on the transfer function correction control signal.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×Mf+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: A clock data recovering circuit solving a problem in which a stable clock signal cannot be extracted is provided. A phase comparator includes a main-signal-discriminator. The main-signal-discriminator discriminates a reception signal by a clock signal to generate recovery data indicating the discrimination result. Phase comparator 2 uses the discrimination result of the main-signal-discriminator to compare phases of a reception signal and a recovery clock and outputs a phase comparison signal indicating the comparison result. A generator generates a recovery clock with a frequency corresponding to the comparison result indicated by the phase comparison signal outputted from phase comparator 2. An eye opening monitor detects an optimal discrimination point of main-signal-discriminator 1 based on a monitor signal split from the reception signal and the recovery data generated by the main-signal-discriminator.

Abstract: An analog-to-digital conversion device which converts an analog input signal into a digital signal and output it includes a signal characteristic detection unit for detecting a predetermined characteristic of the input signal; a control signal generation unit for setting a resolution based on the signal characteristic detected by the signal characteristic detection unit, generating a control signal that indicates only an operation required for performing the analog-to-digital conversion at the resolution, and outputting it; and an analog-to-digital conversion unit for restricting the operation based on the control signal and converting the input signal into the digital signal at the set resolution.