Patents by Inventor Hidemitsu Egawa

Hidemitsu Egawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5992725
    Abstract: An electronic element producing apparatus comprises a bonding tool 1 which has a first supply hole 2 for passing a bonding wire 3 used to bond a bonding pad 6 of a semiconductor device 5 and an external conductor which is to be connected electrically with the bonding pad 6, and contacts a leading end 3b of the bonding wire 3 protruded outside from the first supply hole 2 to the bonding pad 6, and which also has a second supply hole 12 to supply a bonding material to bond the bonding pad 6 and the leading end 3b of the bonding wire 3, the second supply hole 12 being formed to supply the conductive material to a contact point between the bonding wire 3 and the bonding pad 6. Therefore, the bonding pad 6 and the bonding wire 3 can be bonded without applying a dynamic or thermal load to the semiconductor device 5.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: November 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidemitsu Egawa, Hirokazu Ezawa
  • Patent number: 5897361
    Abstract: A trench 13 is formed to isolate a first region 11a and a second region 11b where elements of a semiconductor substrate 11 such as a silicon substrate are formed, and a lamination layer of a first silicon oxide layer 14 having a silicon excess stoichiometry (SiO.sub.x ; 2<x) and a second silicon oxide layer 15 (SiO.sub.2) having an equilibrium composition is filled in the trench 13. The second silicon oxide layer is hydrated. In addition, by heating the semiconductor substrate 11, the first silicon oxide layer 14 is oxidized into the second silicon oxide layer 15 (SiO.sub.2) having an equilibrium composition. At this time, the first silicon oxide layer 14 has its volume expanded while it is oxidized into the second silicon oxide layer 15 having an equilibrium composition, while the second silicon oxide layer 15 is contracted due to dehydration by the heating treatment and removal of a defective lattice.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: April 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidemitsu Egawa
  • Patent number: 5606203
    Abstract: A semiconductor device that includes a wiring line formed from an electrode wiring layer which uses, as an electrode material, an Al alloy containing Cu, wherein wiring line having a size smaller than a crystal grain diameter has a Cu concentration of 0.05 to 0.3 wt %, and a wiring line having a size larger than a crystal grain diameter has a Cu concentration of 0.5 to 10 wt %.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidemitsu Egawa
  • Patent number: 5571578
    Abstract: A plasma CVD device having a chamber, an upper electrode provided in the chamber, an under electrode provided in the chamber to be opposite to the upper electrode and to mount a sample thereon, and a plurality of power sources having a different frequency connected to the upper electrode. Gas is introduced into the chamber of the plasma CVD device, the gas contains at least an organic silicon compound, CF.sub.4 and O.sub.2, and has an element ratio (F/Si) of silicon (Si), constituting the organic silicon compound, to fluorine (F), constituting CF.sub.4, to be set to 15 or more. Si(OC.sub.2 H.sub.5).sub.4 or Si(OCH.sub.3).sub.4 is used as an organic silicon compound.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: November 5, 1996
    Assignee: Kabushiki Kaisha Tohsiba
    Inventors: Naruhiko Kaji, Riichirou Aoki, Hiroyuki Toyama, Hidemitsu Egawa, Takamitsu Yoshida, Yukio Nishiyama
  • Patent number: 5529634
    Abstract: An evaporation chamber for forming fine metal particles is separated from a film formation chamber in which the substrate having a metal film such as a metal column thereon is placed during metal film deposition. The pressure of the film formation chamber is set to be lower than that of the evaporation chamber, and the fine metal particles are sprayed on the substrate by the pressure difference to form the metal column. Therefore, a wiring layer, a connection electrode for connecting the wiring layer to another wiring layer, and the like can easily be formed by a small number of steps.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: June 25, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Miyata, Hidemitsu Egawa, Johta Fukuhara, Shinzi Takeda, Hirokazu Ezawa
  • Patent number: 5068709
    Abstract: A semiconductor device includes a semiconductor pellet, and a metal nitride film or a metal silicide film, each having conductivity and an anti-oxidation property, and being formed on one surface of the pellet to cause the surface to have a substantially uniform potential.
    Type: Grant
    Filed: July 14, 1989
    Date of Patent: November 26, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidemitsu Egawa, Riichirou Aoki, Katsuya Okumura
  • Patent number: 4875088
    Abstract: A semiconductor device includes a semicoonductor pellet, and a metal nitride film or a metal silicide film, each having conductivity and an anti-oxidation property, and being formed on one surface of the pellet to cause the surface to have a substantially uniform potential.
    Type: Grant
    Filed: March 20, 1987
    Date of Patent: October 17, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidemitsu Egawa, Riichirou Aoki, Katsuya Okumura