Abstract: A memory device includes a first memory column, a memory array and a sign decoder. The first memory column is configured to store first sign bits. The memory array is configured to store a first data array and generate bit line signals. The sign decoder is configured to output data signals according to the first sign bits and the bit line signals. The data signals correspond to a second data array, and the first data array is generated by reversing rows of the second data array according to the first sign bits.

Abstract: A read-only memory (ROM) device includes an active region extending along a first direction, and a plurality of gates extending across and over the active region, along a second direction transverse to the first direction. The plurality of gates correspondingly configures, together with the active region, a plurality of transistors. Each of the plurality of transistors is configured to store a datum.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, wherein a first portion of the memory array is accessed during a present cycle, and a second portion of the memory array is to be accessed during a next cycle. The memory circuit includes a decoder configured to provide a next address signal indicating an address of the second portion, and a memory controller operatively coupled to the memory array and the decoder. The decoder is configured to activate, based on the next address signal, the second portion during the present cycle, and cause, based on the next address signal, a third portion of the memory array to operate in a power management mode.

Abstract: A memory device includes a first memory column, a memory array and a sign decoder. The first memory column is configured to store first sign bits. The memory array is configured to store a first data array and generate bit line signals. The sign decoder is configured to output data signals according to the first sign bits and the bit line signals. The data signals correspond to a second data array, and the first data array is generated by reversing rows of the second data array according to the first sign bits.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a maintaining circuit, a sensing circuit, an output circuit, and a verification circuit. The maintaining circuit is configured to maintain data read from a memory cell array and output the data to a data bus in response to a column selection signal. The sensing circuit is configured to sense the data on the data bus in response to at least one sensing enable signal. The output circuit is configured to output the data sensed by the sensing circuit. The verification circuit is configured to verify an operation margin of the sensing circuit and output a verification result. The timing of the at least one sensing enable signal is set according to the verification result of the verification circuit.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a column selection circuit, a sensing circuit, an output circuit, and a verification circuit. The column selection circuit selects n-bit data from data read from a memory cell array according to a column selection signal and outputs the selected n-bit data to an n-bit data bus. The sensing circuit senses the n-bit data on the data bus in response to an activation signal. The output circuit selects m-bit data from the n-bit data sensed by the sensing circuit in response to an internal clock signal synchronized with a serial clock signal applied from outside and outputs the selected m-bit data from output terminals. The verification circuit compares the data sensed by the sensing circuit with the data output by the output circuit to verifying the correctness of read-out data.

Abstract: The invention provides a semiconductor memory device capable of setting input data correctly, including: an input circuit outputting input data to a data bus; a logic circuit outputting the input data on the data bus to digit lines selected by a column address in response to a writing clock signal synchronized with an external clock signal; a page buffer holding data of the digit lines in holding circuits of a column selected by the column address in response to an inner clock signal generated by delaying the writing clock signal, and an address counter generating the column address in response to the writing clock signal. The column address is supplied to the logic circuit in response to the writing clock signal, and the column address is supplied to the page buffer in response to the inner clock signal which has been delayed.

Abstract: A semiconductor memory device and a reading method thereof are provided. A flash memory includes a memory cell array; a page buffer/reading circuit, holding data of a selected page of the memory cell array; a decoding/selecting circuit, selecting n bits data from the data held by the page buffer based on a column address; and a data bus for n bits, which is connected to the decoding/selecting circuit. The decoding/selecting circuit further connects n/2 bits data of an even address to a lower bit position of the data bus and connects n/2 bits data of an odd address to a upper bit position of the data bus based on the column address. When the start address is the odd address, data of the odd address and data of the even address next to the odd address are selected.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a maintaining circuit, a sensing circuit, an output circuit, and a verification circuit. The maintaining circuit is configured to maintain data read from a memory cell array and output the data to a data bus in response to a column selection signal. The sensing circuit is configured to sense the data on the data bus in response to at least one sensing enable signal. The output circuit is configured to output the data sensed by the sensing circuit. The verification circuit is configured to verify an operation margin of the sensing circuit and output a verification result. The timing of the at least one sensing enable signal is set according to the verification result of the verification circuit.

Abstract: The invention provides a semiconductor memory device capable of setting input data correctly, including: an input circuit outputting input data to a data bus; a logic circuit outputting the input data on the data bus to digit lines selected by a column address in response to a writing clock signal synchronized with an external clock signal; a page buffer holding data of the digit lines in holding circuits of a column selected by the column address in response to an inner clock signal generated by delaying the writing clock signal, and an address counter generating the column address in response to the writing clock signal. The column address is supplied to the logic circuit in response to the writing clock signal, and the column address is supplied to the page buffer in response to the inner clock signal which has been delayed.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a column selection circuit, a sensing circuit, an output circuit, and a verification circuit. The column selection circuit selects n-bit data from data read from a memory cell array according to a column selection signal and outputs the selected n-bit data to an n-bit data bus. The sensing circuit senses the n-bit data on the data bus in response to an activation signal. The output circuit selects m-bit data from the n-bit data sensed by the sensing circuit in response to an internal clock signal synchronized with a serial clock signal applied from outside and outputs the selected m-bit data from output terminals. The verification circuit compares the data sensed by the sensing circuit with the data output by the output circuit to verifying the correctness of read-out data.

Abstract: A semiconductor memory device and a reading method thereof are provided. A flash memory includes a memory cell array; a page buffer/reading circuit, holding data of a selected page of the memory cell array; a decoding/selecting circuit, selecting n bits data from the data held by the page buffer based on a column address; and a data bus for n bits, which is connected to the decoding/selecting circuit. The decoding/selecting circuit further connects n/2 bits data of an even address to a lower bit position of the data bus and connects n/2 bits data of an odd address to a upper bit position of the data bus based on the column address. When the start address is the odd address, data of the odd address and data of the even address next to the odd address are selected.

Abstract: A semiconductor memory device and a verification method which can verify data taken inside external terminals are provided. The semiconductor memory device of the invention includes external input/output terminals for inputting or outputting data, a memory array 110 and a page buffer/sensing circuit 170. The page buffer/sensing circuit 170 holds input data inputted from the external input/output terminals and the held input data can be programmed to the memory array 110. Further, the semiconductor memory device includes comparing circuit 132. The comparing circuit 132 compares input data held in the page buffer/sensing circuit 170 and the input data read from the page buffer/sensing circuit 170.

Abstract: A semiconductor device and an output circuit thereof for accelerating rising of a pull-up transistor are provided. The output circuit of the invention includes an external terminal (130), an output buffer (110) and a pre-buffer circuit (120). The external terminal (130) can output output data to an external part. The output buffer (110) is connected to the external terminal (130) and includes a pull-up transistor (Qp1) of P type and a pull-down transistor (Qn1) of N type. The pre-buffer circuit (120) outputs a pull-up signal (PU) and a pull-down signal (PD) corresponding to the output data to the output buffer (110). The pre-buffer circuit (120) also includes a circuit (122). The circuit (122) negatively boosts the pull-up signal (PU) when the pull-up signal (PU) is changed from a high level into a low level.

Abstract: A semiconductor device and an output circuit thereof for accelerating rising of a pull-up transistor are provided. The output circuit of the invention includes an external terminal (130), an output buffer (110) and a pre-buffer circuit (120). The external terminal (130) can output output data to an external part. The output buffer (110) is connected to the external terminal (130) and includes a pull-up transistor (Qp1) of P type and a pull-down transistor (Qn1) of N type. The pre-buffer circuit (120) outputs a pull-up signal (PU) and a pull-down signal (PD) corresponding to the output data to the output buffer (110). The pre-buffer circuit (120) also includes a circuit (122). The circuit (122) negatively boosts the pull-up signal (PU) when the pull-up signal (PU) is changed from a high level into a low level.

Abstract: A semiconductor memory device and a verification method which can verify data taken inside external terminals are provided. The semiconductor memory device of the invention includes external input/output terminals for inputting or outputting data, a memory array 110 and a page buffer/sensing circuit 170. The page buffer/sensing circuit 170 holds input data inputted from the external input/output terminals and the held input data can be programmed to the memory array 110. Further, the semiconductor memory device includes comparing circuit 132. The comparing circuit 132 compares input data held in the page buffer/sensing circuit 170 and the input data read from the page buffer/sensing circuit 170.