Abstract: A mobile phone (10) includes a display (14), an acceleration sensor (54), etc., and a displaying direction of the display (14) is set based on an inclination detected by the acceleration sensor. If the mobile phone (10) is rendered in a horizontal posture or approximately horizontal posture, an image imaged by a first camera module (50) is output so as to be subjected to face detection processing. If a face of a user is detected from the imaged image, a direction of the face is detected. When the face direction is detected, the displaying direction of the display (14) is set based on the face direction. An image is displayed on the display (14) in a displaying direction being set based on the direction of the face of the user.

Abstract: An image pickup apparatus and method operable to reduce flicker is disclosed. A power supply frequency is detected, and a shutter speed is changed. A changed shutter speed value is slower than a calculated shutter speed and that is an integral multiple of 1/(2f), where “f” represents the power supply frequency. One or more still images are captured at the changed shutter speed, and an electronic hand-shake correction is performed in accordance with the captured still images.

Abstract: An electronic apparatus including a drive mechanism, a signal processing section, an image pickup lens, an image pickup device and a focus control section is described. The drive mechanism changes a position of the image pickup lens relative to the image pickup device. The image pickup device outputs an electric signal of an image at each of a plurality of relative positions. The signal processing section processes the electric signal and generates a digital image signal corresponding to the plurality of relative positions. The focus control section extracts, from the digital image signal, high-frequency components for pixels selected from a focus area set in the image of the digital image signal, calculates a focus evaluation value corresponding to each relative position, identifies a maximum focus evaluation value among the calculated focus evaluation values, and moves the image pickup lens to the relative position that provides the maximum focus evaluation value.

Abstract: An image pickup apparatus and method operable to reduce flicker is disclosed. A power supply frequency is detected, and a shutter speed is changed. A changed shutter speed value is slower than a calculated shutter speed and that is an integral multiple of 1/(2f), where “f” represents the power supply frequency. One or more still images are captured at the changed shutter speed, and an electronic hand-shake correction is performed in accordance with the captured still images.

Abstract: An electronic apparatus including a drive mechanism, a signal processing section, an image pickup lens, an image pickup device and a focus control section is described. The drive mechanism changes a position of the image pickup lens relative to the image pickup device. The image pickup device outputs an electric signal of an image at each of a plurality of relative positions. The signal processing section processes the electric signal and generates a digital image signal corresponding to the plurality of relative positions. The focus control section extracts, from the digital image signal, high-frequency components for pixels selected from a focus area set in the image of the digital image signal, calculates a focus evaluation value corresponding to each relative position, identifies a maximum focus evaluation value among the calculated focus evaluation values, and moves the image pickup lens to the relative position that provides the maximum focus evaluation value.

Abstract: A counter 11 continuously reads in the EFM signal from a binarizing circuit 4, resets its count value each time the polarity of the EFM signal changes, counts counter clocks higher in frequency than the EFM signal during each EFM period of the EFM signal, and transfers the count values to a FIFO 12 sequentially. The FIFO 12 temporarily stores the count values transferred, and writes a predetermined number of count values into a buffer RAM 7 in a batch each time the predetermined number of count values are stored.

Abstract: An optical disc signal processing circuit that includes a read data input unit configured to write read data into a buffer memory, the read data being subjected to a scramble process; an error correction processing unit configured to apply an error correction process to the read data read from the buffer memory, the error correction process being a process of performing error correction with an error correction code, and to write into the buffer memory the read data subjected to the error correction process; an external device interface unit configured to read from the buffer memory the read data subjected to the error correction process and apply a descramble process thereto; and a memory copy processing unit configured to read from the buffer memory the read data and apply the descramble process thereto, and to write into the buffer memory the read data subjected to the descramble process.

Abstract: An optical disk apparatus which evaluates an optical disk based on a reproduced signal from the optical disk comprises a delay circuit that has a plurality of first delay elements connected in series which have a binarized signal of the reproduced signal supplied to one end of the series and delay the binarized signal in a sequence to the other end, a data hold circuit that holds level data of the binarized signal obtained from at least one of the plurality of first delay elements of the delay circuit, and a processor that determines whether the binarized signal is at one level or at the other level based on the level data.

Abstract: An optical disk apparatus irradiating a laser beam to an optical disk and receiving reflected light of the laser beam changed by marks recorded on the optical disk to perform evaluation of the optical disk based on a regeneration signal corresponding to an amount of light of the reflected light, the apparatus comprising a measurement circuit, based on a relationship that phases substantially match between a first timing of each of a rising edge and falling edge in a binarized signal of the regeneration signal and a second timing of a rising edge or falling edge in a synchronized clock signal conforming in phase to the binarized signal, measuring a phase difference between the first timing and a third timing of the synchronized clock signal shifted by a predetermined phase of the synchronized clock signal from the second timing as a reference.

Abstract: To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to error correction encoding of a PI direction, error correction encoding of a PO direction is carried out at a PO arithmetic operation circuit (105), and an obtained PO code is added to corresponding data and written in a memory (101). Subsequently, data are read line by line in a PI direction from the memory (101) to a PI arithmetic operation circuit (110), a PI code is added to the data, and the data are sequentially output to a modulation circuit (200). Thus, it is possible to omit memory access when the data is read from the memory (101) to the modulation circuit (200) and memory access when the error correction code is written in the memory by the PI arithmetic operation circuit.

Abstract: To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to its writing in a memory (101), data from a host is processed by an EDC arithmetic operation circuit (110) and a scrambling arithmetic operation circuit (111), and written in the memory (101). Next, error correction encoding of a PO direction is executed at a PO arithmetic operation circuit (105), and an obtained PO code is added to corresponding data to be written in the memory (101). Subsequently, the data are read in a PI direction line by line from the memory (101) to a PI arithmetic operation circuit (112). A PI code is added to the data, and the data are sequentially output to a modulation circuit (200).

Abstract: To provide a data encoding circuit capable of securing real-timeness of a recording operation even in a memory of a low operation clock frequency by reducing the number of times of accessing the memory, and simultaneously reducing power consumption and memory costs. Prior to its writing in a memory (101), data from a host is input to an EDC arithmetic operation circuit (110) and a scrambling arithmetic operation circuit (111) to be processed, and then the error correction codes are added to the data written in the memory (101) from the scrambling arithmetic operation circuit (111) by a PI arithmetic operation circuit (104) and a PO arithmetic operation circuit (105). Accordingly, it is possible to omit memory access when the data is written from the host in the memory, and memory access when the data is read from the memory to the EDC arithmetic operation circuit. Thus, it is possible to reduce an operation clock frequency of the memory (101).

Abstract: A counter 11 continuously reads in the EFM signal from a binarizing circuit 4, resets its count value each time the polarity of the EFM signal changes, counts counter clocks higher in frequency than the EFM signal during each EFM period of the EFM signal, and transfers the count values to a FIFO 12 sequentially. The FIFO 12 temporarily stores the count values transferred, and writes a predetermined number of count values into a buffer RAM 7 in a batch each time the predetermined number of count values are stored.