Patents by Inventor Hidenao Iwane

Hidenao Iwane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9614401
    Abstract: A control server according to an embodiment sorts a plurality of notebook PCs into a plurality of groups so that the total value of the remaining energy is a value similar to the total value of the remaining energy of the rechargeable batteries of a plurality of notebook PCs included in a different group. The control server according to the embodiment performs local search individually on the sorted groups, and generates a control plan for the individual notebook PCs.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 4, 2017
    Assignees: FUJITSU LIMITED, THE UNIVERSITY OF TOKYO
    Inventors: Hitoshi Yanami, Hidenao Iwane, Tomotake Sasaki, Hirokazu Anai, Junji Kaneko, Shinji Hara, Suguru Fujita
  • Publication number: 20160091541
    Abstract: A parameter determination method is disclosed. Information of specification of the output is received. A first circuit constant and a second circuit constant to set in elements forming an equivalent circuit of the predetermined circuit is received. A first range of a plurality of the parameters which are to be set in a compensator that compensates the output is specified based on the information of the specification and the first circuit constant. A second range of a plurality of parameters which are to be set in the compensator is specified based on the information of the specification and the second circuit constant. At least one of a parameter included in both the first range and the second range.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 31, 2016
    Inventors: Yoshinobu Matsui, Hirokazu Anai, Hidenao Iwane
  • Patent number: 8935131
    Abstract: When model expressions of objective functions are generated at vertexes of a quadrilateral on a plane concerning P and N channels of transistors in SRAM, the initial number of times of simulation is allocated to each objective function at each designated vertex according to weight values set based on relationships presumed among the objective functions at each designated vertex. For each objective function at each designated vertex, first simulation is executed the allocated number of times. Furthermore, a model expression is generated from the first simulation result, and an evaluation indicator of an approximation accuracy of the model expression is calculated. Then, for each model expression, it is determined whether the corresponding model expression has influence on the yield, and based on the evaluation indicator of the corresponding model expression and presence or absence of the influence, it is determined whether additional simulation is required for the corresponding objective function.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Limited
    Inventors: Hidenao Iwane, Hirokazu Anai, Hitoshi Yanami
  • Patent number: 8843351
    Abstract: This method includes: generating a constraint equation from data of an approximate expression of a cost function representing a relationship between a plurality of design parameters and a cost, data of a route in a cost space and data of a search range in a design parameter space; obtaining a logical expression of a solution for the constraint equation from a quantifier elimination processing unit that carries out a processing according to a quantifier elimination method; substituting coordinates of each of a plurality of points within the search range in the design parameter space into the logical expression of the solution to determine, for each of the plurality of points, true or false of the logical expression of the solution; and displaying the design parameter space in which a display object including a first point for which true is determined is disposed at the first point.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Yanami, Hirokazu Anai, Hidenao Iwane
  • Publication number: 20140249793
    Abstract: A control server according to an embodiment sorts a plurality of notebook PCs into a plurality of groups so that the total value of the remaining amounts is a value similar to the total value of the remaining amounts of the rechargeable batteries of a plurality of notebook PCs included in a different group. The control server according to the embodiment performs local search individually on the sorted groups, and generates a control plan for the individual notebook PCs.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 4, 2014
    Applicants: The University of Tokyo, FUJITSU LIMITED
    Inventors: Hitoshi Yanami, Hidenao Iwane, Tomotake Sasaki, Hirokazu Anai, Junji Kaneko, Shinji Hara, Suguru Fujita
  • Patent number: 8676548
    Abstract: A design support apparatus for determining a plurality of objective functions for modeling an object having a plurality of elements, each of the elements providing variable geometrical parameters, the design support apparatus includes a memory for storing the variable geometrical parameters and a processor for executing a process including: determining boundary information associated with specified geometrical parameters of the elements which indicate a state of contact between the elements, dividing the variable geometrical parameters into a plurality of groups on the basis of the boundary information, and determining the plurality of objective functions for each of the groups by using the variable geometrical parameters.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Yanami, Hirokazu Anai, Tsuneo Nakata, Hidenao Iwane
  • Patent number: 8533653
    Abstract: A design support apparatus includes: a logical expression substitution unit to substitute a part of the logical expression, which includes a function expression of the design variables and a quantifier attached to the design variable, with a substitution variable; a quantifier elimination unit to generate a relational expression including the substitution variable and design variables without the quantifier by eliminating the design variable to which the quantifier is attached from the logical expression; a sampling point generation unit to generate a plurality of sampling points corresponding to the design variables and the substitution variable included in the relational expression; a possible range computation unit to compute, for each of the sampling points, a possible range that the relational expression may take, by calculating values of remaining design variables included in the relational expression based on the relational expression; and a possible range display unit to display the possible range.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Limited
    Inventors: Hirokazu Anai, Hidenao Iwane, Hitoshi Yanami
  • Patent number: 8498844
    Abstract: A first model expression having a first order and representing a relationship between evaluation indicators and the design parameters and a second model expression having a second order higher than the first order and representing a relationship between them are generated. Then, according to a quantifier elimination method, values of the design parameters, which realize an optimum solution of the first model expression, are calculated. And, a design parameter whose value is identical to an upper limit value or a lower limit value is identified, and the second model expression is transformed by substituting the upper limit value or the lower limit value, as a value of the identified design parameter, for the second model expression. Finally, according to the quantifier elimination method, values of the design parameters in the transformed second model expression, which realize an optimum solution of the transformed second model expression, is calculated.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Limited
    Inventors: Hidenao Iwane, Hirokazu Anai, Hitoshi Yanami
  • Publication number: 20130054659
    Abstract: The disclosed method includes: generating a problem for a quantifier elimination (QE) method from a cost function representing a relationship between a parameter set and a cost; executing, by a module that executes a processing for the QE method by term substitution, a processing for the problem, to obtain a first processing result; when the first processing result includes a first partial problem for which the term substitution is impossible, executing, by a module that execute a numerical analysis processing, a processing to minimize the cost for the first partial problem, to obtain a second processing result; when the first processing result includes a logical expression as a solution of a second partial problem for which the term substitution has been completed, generating data to identify a minimum cost value from the logical expression; and generating a minimum cost for the problem from at least the second processing result.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 28, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi YANAMI, Hirokazu ANAI, Hidenao IWANE
  • Publication number: 20130046467
    Abstract: The disclosed method includes: first identifying, for each candidate place of a second place that will be traveled subsequently to a first place whose traveling order has been determined among plural places and for which traveling order is not determined, a point in a space mapped by a travel cost and one or plural costs, by reading out a travel cost value between the first place and the candidate place, and reading one or plural cost values of the candidate place from a second data storage unit; extracting one or plural candidate places corresponding to Pareto solutions in the space; second identifying the second place from the one or plural extracted candidate places; and generating traveling route candidates for the plural places by repeating the first identifying, the extracting and the second identifying.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Hidenao Iwane, Kazuhiro Matsumoto
  • Patent number: 8364450
    Abstract: An embodiment relates to a multi-objective optimization design supporting technique to reduces the computational complexity of QE/CAD. When the input logical expression generated by a logical-expression-with-qualifier generation unit is satisfied in regard to the sample point included in a certain piece of cell information for each value of the same design parameter, a first cell processing unit does not evaluate the input logical expression on the cell information including other sample points having a value equal to or smaller than the value of a predetermined design variable (for example, a design variable indicating a yield) corresponding to the sample point above, but selects it as the cell information for an output of a logical expression without a qualifier.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: January 29, 2013
    Assignee: Fujitsu Limited
    Inventors: Hidenao Iwane, Hirokazu Anai, Hitoshi Yanami
  • Publication number: 20130024227
    Abstract: A disclosed method includes determining, for each operator group, scheduled execution order by arranging, for each operator group, the predetermined number of operations to be conducted while traveling, wherein at least a portion of the predetermined number of operations is allotted to each of the operator groups; determining, for each operator group, operations to be conducted in the scheduled execution order by determining, for each operator group, along the scheduled execution order of the operator group and while advancing time, whether movement to an operation place of each operation of the predetermined number of operations and start of the operation satisfy a constraint condition set in advance for the predetermined number of operations; and calculating a first evaluation value of orders of the operations determined to be conducted for the plural operator groups.
    Type: Application
    Filed: June 20, 2012
    Publication date: January 24, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Hidenao IWANE, Akifumi Kira
  • Publication number: 20120046915
    Abstract: This method includes: generating a constraint equation from data of an approximate expression of a cost function representing a relationship between a plurality of design parameters and a cost, data of a route in a cost space and data of a search range in a design parameter space; obtaining a logical expression of a solution for the constraint equation from a quantifier elimination processing unit that carries out a processing according to a quantifier elimination method; substituting coordinates of each of a plurality of points within the search range in the design parameter space into the logical expression of the solution to determine, for each of the plurality of points, true or false of the logical expression of the solution; and displaying the design parameter space in which a display object including a first point for which true is determined is disposed at the first point.
    Type: Application
    Filed: May 25, 2011
    Publication date: February 23, 2012
    Applicant: Fujitsu Limited
    Inventors: Hitoshi YANAMI, Hirokazu Anai, Hidenao Iwane
  • Publication number: 20110295573
    Abstract: When model expressions of objective functions are generated at vertexes of a quadrilateral on a plane concerning P and N channels of transistors in SRAM, the initial number of times of simulation is allocated to each objective function at each designated vertex according to weight values set based on relationships presumed among the objective functions at each designated vertex. For each objective function at each designated vertex, first simulation is executed the allocated number of times. Furthermore, a model expression is generated from the first simulation result, and an evaluation indicator of an approximation accuracy of the model expression is calculated. Then, for each model expression, it is determined whether the corresponding model expression has influence on the yield, and based on the evaluation indicator of the corresponding model expression and presence or absence of the influence, it is determined whether additional simulation is required for the corresponding objective function.
    Type: Application
    Filed: March 25, 2011
    Publication date: December 1, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Hidenao Iwane, Hirokazu Anai, Hitoshi Yanami
  • Publication number: 20110184706
    Abstract: A first model expression having a first order and representing a relationship between evaluation indicators and the design parameters and a second model expression having a second order higher than the first order and representing a relationship between them are generated. Then, according to a quantifier elimination method, values of said design parameters, which realize an optimum solution of the first model expression, are calculated. And, a design parameter whose value is identical to an upper limit value or a lower limit value is identified, and the second model expression is transformed by substituting the upper limit value or the lower limit value, as a value of the identified design parameter, for the second model expression. Finally, according to the quantifier elimination method, values of the design parameters in the transformed second model expression, which realize an optimum solution of the transformed second model expression, is calculated.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 28, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Hidenao IWANE, Hirokazu Ani, Hitoshi Yanami
  • Publication number: 20110148867
    Abstract: A shape optimization method includes: obtaining parameter data including data concerning a first relational expression that causes coordinate values of plural vertexes in at least a portion of an object to be changed together and includes a parameter capable of setting values from outside; determining, according to a predetermined algorithm, a value of the parameter in the parameter data; calculating coordinates values of the plural vertexes from a second relational expression determined by the first relational expression and the determined value of the parameter; generating shape data including coordinate values of first vertexes to define the shape of the object from initial coordinate values and the calculated coordinate values; causing to execute cost calculation of the shape defined by the shape data; and outputting shape data in case of a best result of the cost calculation after repeating the aforementioned processing based on a result of the cost calculation.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 23, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi YANAMI, Hirokazu ANAI, Hidenao IWANE
  • Publication number: 20110022365
    Abstract: An embodiment relates to a multi-objective optimization design supporting technique to reduces the computational complexity of QE/CAD. When the input logical expression generated by a logical-expression-with-qualifier generation unit is satisfied in regard to the sample point included in a certain piece of cell information for each value of the same design parameter, a first cell processing unit does not evaluate the input logical expression on the cell information including other sample points having a value equal to or smaller than the value of a predetermined design variable (for example, a design variable indicating a yield) corresponding to the sample point above, but selects it as the cell information for an output of a logical expression without a qualifier.
    Type: Application
    Filed: July 19, 2010
    Publication date: January 27, 2011
    Applicant: Fujitsu Limited
    Inventors: Hidenao IWANE, Hirokazu Anai, Hitoshi Yanami
  • Publication number: 20100332195
    Abstract: A design support apparatus includes a parameter set generation unit configured to obtain a plurality of types of parameters and sequentially generates parameter sets while sequentially changing each parameter, a design object shape data generation unit configured to generate design object shape data based on the parameter set and initial shape data representing an initial shape of the design object shape, a geometric penalty function value calculation unit configured to calculate a geometric penalty function value indicating suitability of geometric characteristics of the design object shape based on the design object shape data, an objective function calculation control unit configured to determine whether or not the parameter set is used to calculate an objective function based on the geometric penalty function value and an optimal value of the objective function, and an objective function calculation unit configured to calculate the objective function based on the parameter set.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi YANAMI, Hirokazu Anai, Hidenao Iwane, Tsuneo Nakata
  • Publication number: 20100205574
    Abstract: A design support apparatus includes: a logical expression substitution unit to substitute a part of the logical expression, which includes a function expression of the design variables and a quantifier attached to the design variable, with a substitution variable; a quantifier elimination unit to generate a relational expression including the substitution variable and design variables without the quantifier by eliminating the design variable to which the quantifier is attached from the logical expression; a sampling point generation unit to generate a plurality of sampling points corresponding to the design variables and the substitution variable included in the relational expression; a possible range computation unit to compute, for each of the sampling points, a possible range that the relational expression may take, by calculating values of remaining design variables included in the relational expression based on the relational expression; and a possible range display unit to display the possible range.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 12, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Hirokazu ANAI, Hidenao Iwane, Hitoshi Yanami
  • Publication number: 20100153074
    Abstract: A design support apparatus for determining a plurality of objective functions for modeling an object having a plurality of elements, each of the elements providing variable geometrical parameters, the design support apparatus includes a memory for storing the variable geometrical parameters and a processor for executing a process including: determining boundary information associated with specified geometrical parameters of the elements which indicate a state of contact between the elements, dividing the variable geometrical parameters into a plurality of groups on the basis of the boundary information, and determining the plurality of objective functions for each of the groups by using the variable geometrical parameters.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 17, 2010
    Applicant: Fujitsu Limited
    Inventors: Hitoshi YANAMI, Hirokazu Anai, Tsuneo Nakata, Hidenao Iwane