Abstract: An integrated circuit design apparatus is provided with a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing the variations of the power supply voltages with first and second reference levels, the second reference level being smaller than the first reference level; a redesign module adapted to redesign the target circuit when at least one of the variations of the power supply voltages is larger than the first reference level; a delay variation calculation module adapted to correct circuit delay data of the respective instances based on the variations of the power supply voltages of the respective instances; a static timing analysis tool performing timing verification of the target integrated circuit.

Abstract: The semiconductor integrated circuit device includes a plurality of decoupling cells that suppress power noise respectively, a plurality of power switches that connect the decoupling cells to a power line respectively, and a control circuit that controls the number of power switches selected from among the plurality of power switches and to be turned on according to power noise to be changed according to the operation state of each of internal circuits driven by a power supplied from the power line.

Abstract: A voltage variation reducing circuit includes a first transistor and a second transistor. The first transistor is connected to a first power source line of a first power source voltage at a source and a second power source line of a second power source voltage at a drain and a gate. The second transistor is connected to a third power source line of a third power source voltage higher than the second power source voltage at a source and the second power source line at a drain gate.

Abstract: Aiming to efficiently preventing an increase in power supply noise caused by a variation in consumption current, a semiconductor integrated circuit device of the present invention includes: first and second power supply interconnections that provide power supply to an internal circuit; a power switch that connects the first power supply interconnection and the second power supply interconnection to each other; power supply noise measurement circuits that measure power supply noise of the internal circuit; and a control circuit that controls a conduction state of the power switch on the basis of a result of a measurement performed by the power supply noise measurement circuits.

Abstract: The semiconductor integrated circuit device includes a plurality of decoupling cells that suppress power noise respectively, a plurality of power switches that connect the decoupling cells to a power line respectively, and a control circuit that controls the number of power switches selected from among the plurality of power switches and to be turned on according to power noise to be changed according to the operation state of each of internal circuits driven by a power supplied from the power line.

Abstract: An integrated circuit design apparatus is provided with a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing the variations of the power supply voltages with first and second reference levels, the second reference level being smaller than the first reference level; a redesign module adapted to redesign the target circuit when at least one of the variations of the power supply voltages is larger than the first reference level; a delay variation calculation module adapted to correct circuit delay data of the respective instances based on the variations of the power supply voltages of the respective instances; a static timing analysis tool performing timing verification of the target integrated circuit.