Abstract: The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC0 through QPCm) to each of main bit lines (MB0 through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC). In parallel with it, sub bit lines (LB00 through LBkm) are respectively discharged by discharge elements (QD00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a non-volatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.

Abstract: The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC0 through QPCm) to each of main bit lines (MB0 through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC) In parallel with it, sub bit lines (LB00 through LBkm) are respectively discharged by discharge elements (QD00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a nonvolatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.

Abstract: The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC0 through QPCm) to each of main bit lines (MB0 through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC). In parallel with it, sub bit lines (LB00 through LBkm) are respectively discharged by discharge elements (QD00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a non-volatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.

Abstract: In order to make any voltage imbalance between the winding circuits of each phase small and to simplify the edge structure of the armature winding, in a rotating electric machine of four poles, having slots of 9n (1≦n≦7) pieces provided for the stator core with a double-layer winding per each slot, and an armature winding of three-phase star connection being constituted with three winding circuits connected in parallel in each phase, two of the four poles of each phase are constituted with only one of the three winding circuits.