Abstract: The semiconductor memory system includes a first semiconductor memory device, a second semiconductor memory device and a controller. The first memory device is arranged so that data reading and writing at high speeds is performed through the interface of the buses connected to the address inputs and the data I/O ports. The second memory device is arranged so that data reading and writing is controlled by commands provided via the data I/O ports. The controller is arranged responsive to commands from a CPU for controlling the read and write operation of each of the memory devices. In this system, a single write operation of the CPU to the controller can simultaneously write the same data into the memory devices. Accordingly, the time required for data reading and writing on a plurality of memory devices can be minimized, and thus the efficiency of its overall operation can be increased.

Abstract: The semiconductor memory system includes a first semiconductor memory device, a second semiconductor memory device and a controller. The first memory device is arranged so that data reading and writing at high speeds is performed through the interface of the buses connected to the address inputs and the data I/O ports. The second memory device is arranged so that data reading and writing is controlled by commands provided via the data I/O ports. The controller is arranged responsive to commands from a CPU for controlling the read and write operation of each of the memory devices. In this system, a single write operation of the CPU to the controller can simultaneously write the same data into the memory devices. Accordingly, the time required for data reading and writing on a plurality of memory devices can be minimized, and thus the efficiency of its overall operation can be increased.

Abstract: A PC card wherein a voltage supplied by an auxiliary battery is confirmable from an external device in a state in which an interface is maintained. A selection signal from an address decode circuit changes to a significant condition when a given address in an unused memory area is accessed in accordance with an address signal, with the result that a MOSFET transistor turns on so that the auxiliary battery makes contact with a voltage detector to detect the voltage of the auxiliary battery. The detection result is temporarily stored in a register and output as a portion of data to the external device at the time that a register output enable signal changes to a significant condition by an output enable signal.

Abstract: An IC card includes a first auxiliary read-only memory containing identification data and a second auxiliary read/write memory. Under control of a host system, a write operation is performed into both the first and second auxiliary memories and only the data in the second auxiliary memory is updated. The host system reads the data from each of the first and second auxiliary memories and a data matching block in the host system checks each of the data against the data in a memory in the host system. Access to the main memory of the IC card is authorized only when the checking results in a match.

Abstract: A PC card including a PCMCIA interference connected to external system equipment, a communication control section for communication through an external line, and a memory control section connected to a memory device. The PC card also includes an internal bus including a data bus, an address bus and a control signal bus connects a plurality of functions in the PC card, that is, the PCMCIA interface, the communication control section and the memory control section, to each other. By providing the control signal bus for various control signals, the PC card can be used in various modes. For example, in one mode, the PC card can be used in various modes. For example, in one mode, the PC card can be used as a communication card or a memory card. In another mode, data can be transferred through the internal bus between the communication control section and the memory control section. In yet another mode, the PC card can be used as a communication card and a memory card in a time-sharing manner.

Abstract: A semiconductor module includes a plurality of circuit boards superposed one on another, each circuit board having two opposed surfaces; and groups of electronic parts mounted on the two opposed surfaces of each of the circuit boards, the groups of electronic parts including IC packages, each IC package having a package body and leads extending outward from at least one side surface of the package body, wherein the IC packages mounted between an adjacent pair of the circuit boards in a back-to-back relationship are located on the circuit board so that the leads of one of the IC packages on one of the circuit boards are directly opposite the package body of an IC package on the other of the circuit boards.

Abstract: A semiconductor data storage device includes both volatile and non-volatile semiconductor data storage elements and prevents erroneous writing of data and contention of data at the time of connection and disconnection of an external power source. When the external power source is connected to or disconnected from the semiconductor data storage device in accordance with a reset signal of a power control circuit detecting a voltage, a card enable signal line, an output enable signal line, and a write enable signal line are forcibly deactivated for a predetermined period of time by a delay circuit and gate circuits.

Abstract: In a semiconductor memory controller there are provided in parallel N-bit even number and odd number byte address decoder circuits, a 2N-bit address decoder circuit, even number and odd number byte subaddress decoder circuits for semiconductor memories having smaller capacities than semiconductor memories connected to the even and odd number byte subaddress decoder circuits and the 2N-bit address decoder circuit. The semiconductor memories are controlled to form a continuous address space. Signal levels are controlled by a pass through current preventing input buffer circuit, a three state output buffer circuit, and a backup state control circuit. Thereby, semiconductor memories different from each other in volatile/non-volatile type, memory capacity, and data bus width can be controlled even in a mixed state and unnecessary power consumption due to pass through power is significantly reduced.

Abstract: A semiconductor module including a plurality of circuit boards, each circuit board having two opposed surfaces on which IC packages having leads extending outward through upper or lower portions of side surfaces are mounted. The circuit boards are superposed one on another and the IC packages are arranged to prevent contact between the leads of the IC packages disposed close to or in contact with each other in a back-to-back relationship between each adjacent pair of circuit boards. The IC packages mounted between each adjacent pair of circuit boards in a back-to-back relationship are upper lead type IC packages on one of the circuit boards and lower lead type IC packages on the other circuit board.

Abstract: A memory control circuit for controlling a memory chip enable signal without unnecessary power consumption in a non-volatile memory chip during the backup state. When a backup signal (BUP) shows that the card is in a backup state, all of the memory chip enable signal output lines are set to a high-impedance state by controlling a backup time control means inserted therein, and pull-up resistors 20 are connected to the memory chip enable signal output lines 8 connected to the volatile memory chip 2 for setting them to a "H" level, and an A power source 5 without backup is connected to the memory chip enable signal output lines 8 connected to the non-volatile memory chip 3 through a pull-up resistor 30, thereby preventing unnecessary current from flowing.

Abstract: An input/output control circuit for an IC card equipped with one-time programmable read only memory integrated circuits (PROM-ICs) includes a read data bus buffer connected between the one-time PROM-ICs and a data bus; a write data bus buffer connected between the one time PROM-ICs and the data bus; and a selection device for detecting the power supply voltage supplied to the one-time PROM-ICs and selecting one of the read data bus buffer and the write data bus buffer in response to the detected power supply voltage. The input/output control circuit improves the ability of the IC card to withstand electrostatic discharge and prevents the electrical characteristics of an IC card from changing with a change in the number of one-time PROM-ICs mounted thereon.

Abstract: A portable semiconductor memory unit comprises a semiconductor memory requiring different voltages for reading and writing. A single supply voltage is supplied to the portable semiconductor memory unit from an external terminal equipment and transformed by a transforming circuit provided in the portable semiconductor memory unit with necessity to be applied to the semiconductor memory. Thus, the terminal equipment does not need to be installed with a dedicated voltage supply circuit for generating different level voltages.

Abstract: An IC card with a bus structure switchable between a narrow bus mode (such as an 8 bit bus) and a wide bus mode (such as a 16 bit bus). A plurality of memories are provided (in the example preferably 8 bit memories). Addresses are coupled to the IC card for activating the memories in parallel when in the wide bus mode or in selectable sequence when in the narrow bus mode. The data lines of the memories are connected by bus switching means to couple the memory data lines to the output bus so that data exchange is in parallel between both of the memories and the 16-bit bus in the wide bus mode, and is between individual ones of the memories and only the 8-bit bus in the narrow bus mode. The result is efficient use of both semiconductor memories in both the wide bus and narrow bus modes, with automatic switching between modes on the IC card in dependence upon a logic signal derived from the external terminal which defines the mode in which the IC card is intended to operate.