Abstract: A method for manufacturing an active matrix substrate includes: (A) a step of forming a laminated film including a lower conductive film, a lower insulating film, and a semiconductor film in this order on a substrate; (B) a step of forming a first resist layer; (C) a step of performing a patterning on the laminated film, the step including, in the first formation region, forming the first substructure including a first lower conductive layer, a first lower insulating layer, and a first semiconductor layer respectively formed from the lower conductive film, the lower insulating film, and the semiconductor film, and (D) a step of forming source and drain electrodes electrically connected to the first semiconductor layer.

Abstract: A method for manufacturing an active matrix substrate includes: (A) a step of forming a laminated film including a lower conductive film, a lower insulating film, and a semiconductor film in this order on a substrate; (B) a step of forming a first resist layer; (C) a step of performing a patterning on the laminated film, the step including, in the first formation region, forming the first substructure including a first lower conductive layer, a first lower insulating layer, and a first semiconductor layer respectively formed from the lower conductive film, the lower insulating film, and the semiconductor film, and (D) a step of forming source and drain electrodes electrically connected to the first semiconductor layer.

Abstract: An active matrix substrate includes a thin film transistor having a gate electrode, an oxide semiconductor layer disposed on the gate electrode via a gate insulating layer, and a source electrode and a drain electrode disposed on the oxide semiconductor layer. A plurality of gate bus lines and the gate electrode are made of a first electrically conductive film. At least part of each of the plurality of source bus lines, the source electrode, and the drain electrode have a multilayer structure including a lower layer that is made of a second electrically conductive film and an upper layer that is made of a first transparent electrically conductive film. Between the plurality of source bus lines and the gate insulating layer, a plurality of first oxide strips extending along the first direction are disposed, the first oxide strips being made of the same oxide semiconductor film as the oxide semiconductor layer.

Abstract: A liquid crystal display panel (100) according to the present invention includes a plurality of spacers configured to hold a gap between a first substrate (10) and a second substrate (30). The plurality of spacers include a plurality of first spacers in a display region and a plurality of second spacers (55) in a non-display region. The first substrate includes a first metal layer (12) and a second metal layer (16), a first transparent conductive layer (22) formed on the second metal layer and in direct contact with the second metal layer, a second inorganic insulating layer (23) formed on the first transparent conductive layer, and an organic insulating layer (25) formed on the second inorganic insulating layer. When viewed from the normal direction of the first substrate, each of the plurality of spacers overlaps with the first transparent conductive layer and the second inorganic insulating layer, and overlaps with the first metal layer and/or the second metal layer.

Abstract: An active matrix substrate includes a thin film transistor having a gate electrode, an oxide semiconductor layer disposed on the gate electrode via a gate insulating layer, and a source electrode and a drain electrode disposed on the oxide semiconductor layer. A plurality of gate bus lines and the gate electrode are made of a first electrically conductive film. At least part of each of the plurality of source bus lines, the source electrode, and the drain electrode have a multilayer structure including a lower layer that is made of a second electrically conductive film and an upper layer that is made of a first transparent electrically conductive film. Between the plurality of source bus lines and the gate insulating layer, a plurality of first oxide strips extending along the first direction are disposed, the first oxide strips being made of the same oxide semiconductor film as the oxide semiconductor layer.

Abstract: An active matrix substrate of a liquid crystal panel of an FFS mode includes gate lines, data lines, pixel circuits each including a switching element and a pixel electrode, a protective insulating film formed in a layer over these elements, and a common electrode formed in a layer over the protective insulating film. The data line includes a lower layer conductor part formed using indium tin oxide together with the pixel electrode, and an upper layer conductor part formed using molybdenum niobium and an aluminum alloy. The lower layer conductor part is formed in a disconnected shape at a position of the switching element, and the upper layer conductor part is formed in a continuous shape so as to overlap with the lower layer conductor part. With this, an active matrix substrate capable of preventing a disconnection failure of the data line and an alignment failure is provided.

Abstract: A liquid crystal display panel (100) according to the present invention includes a plurality of spacers configured to hold a gap between a first substrate (10) and a second substrate (30). The plurality of spacers include a plurality of first spacers in a display region and a plurality of second spacers (55) in a non-display region. The first substrate includes a first metal layer (12) and a second metal layer (16), a first transparent conductive layer (22) formed on the second metal layer and in direct contact with the second metal layer, a second inorganic insulating layer (23) formed on the first transparent conductive layer, and an organic insulating layer (25) formed on the second inorganic insulating layer. When viewed from the normal direction of the first substrate, each of the plurality of spacers overlaps with the first transparent conductive layer and the second inorganic insulating layer, and overlaps with the first metal layer and/or the second metal layer.

Abstract: There are provided a display device including a highly reliable wiring having excellent adhesion to an insulating film, and a method for manufacturing the same. A molybdenum-niobium layer has good adhesion to an insulating film, and thus, a first wiring having the molybdenum-niobium layer as an upper layer wiring is tightly adhered to a gate insulating film which is formed on the surface of the upper layer wiring. When there is a need to exchange a semiconductor chip mounted on a connection terminal that is provided at an end portion of a wiring such as a gate lead line or a source lead line formed of the first wiring, an ACF which was used for pressure-bonding of the semiconductor chip remains on the connection terminal even if the semiconductor chip is peeled off.

Abstract: A liquid crystal display panel includes: a first substrate; a second substrate; a liquid crystal layer provided between the first substrate and the second substrate; and a plurality of spacers configured to hold a gap between the first substrate and the second substrate. The first substrate includes: a plurality of TFTs; a plurality of first wiring lines including part of a first metal layer; a plurality of second wiring lines including part of a second metal layer; an inorganic insulating layer formed on the second metal layer; a first transparent conductive layer formed below the inorganic insulating layer; a second transparent conductive layer formed on the inorganic insulating layer; and an organic insulating layer formed on the inorganic insulating layer. Each of the plurality of spacers overlaps with at least one of a source electrode and a drain electrode of a corresponding one of the plurality of TFTs, and each of the plurality of spacers includes a part of the organic insulating layer.

Abstract: An active matrix substrate for a liquid crystal panel of an FFS mode includes a plurality of connecting units in a connecting region in order to electrically connect a common electrode, a first common main wiring 31, and a second common main wiring 32. The connecting unit includes a contact hole 41 that connects a connecting electrode 37 and the first common main wiring 31, the connecting electrode 37 formed integrally with the common electrode, and a contact hole 42 that connects the connecting electrode 37 and the second common main wiring 32. An amorphous Si film 122 of the second common main wiring 32 is formed larger than a main conductor part 131 of the second common main wiring 32 in a position of the contact hole 41, and is covered with SiNx films 151, 152 that are protective insulating films. This prevents the connecting electrode from having a step disconnection at a pattern end of the common main wiring.

Abstract: An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.

Abstract: An active matrix substrate for a liquid crystal panel of an FFS mode includes a plurality of connecting units in a connecting region in order to electrically connect a common electrode, a first common main wiring 31, and a second common main wiring 32. The connecting unit includes a contact hole 41 that connects a connecting electrode 37 and the first common main wiring 31, the connecting electrode 37 formed integrally with the common electrode, and a contact hole 42 that connects the connecting electrode 37 and the second common main wiring 32. An amorphous Si film 122 of the second common main wiring 32 is formed larger than a main conductor part 131 of the second common main wiring 32 in a position of the contact hole 41, and is covered with SiNx films 151, 152 that are protective insulating films. This prevents the connecting electrode from having a step disconnection at a pattern end of the common main wiring.

Abstract: An active matrix substrate for a liquid crystal panel of an FFS mode includes gate lines, data lines, pixel circuits each including a switching element and a pixel electrode, a protective insulating film formed in a layer over these elements, and a common electrode 30 formed in a layer over the protective insulating film. The common electrode 30 has slits 31 corresponding to the pixel electrode, for generating a lateral electric field to be applied to a liquid crystal layer. In the common electrode 30, a cutout above data line 32 having a portion extending in the same direction as that of the data line is formed in a region including a part of a placement region for the data line. On a counter substrate, a black matrix is formed in a position that faces a region including placement regions for the gate line, the data line, the switching element, and the cutout above data line 32. This reduces display failure caused by a load of the data line.

Abstract: There are provided a display device including a highly reliable wiring having excellent adhesion to an insulating film, and a method for manufacturing the same. A molybdenum-niobium layer has good adhesion to an insulating film, and thus, a first wiring having the molybdenum-niobium layer as an upper layer wiring is tightly adhered to a gate insulating film which is formed on the surface of the upper layer wiring. When there is a need to exchange a semiconductor chip mounted on a connection terminal that is provided at an end portion of a wiring such as a gate lead line or a source lead line formed of the first wiring, an ACF which was used for pressure-bonding of the semiconductor chip remains on the connection terminal even if the semiconductor chip is peeled off.

Abstract: An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.

Abstract: A first wiring of the present invention is a wiring having a two-layer structure including a lower layer wiring and an upper layer wiring which is formed to cover an upper surface and both side surfaces of the lower layer wiring, and thus, even if the lower layer wiring includes a part where the line width is reduced and which is nearly disconnected due to a particle or the like attached at the time of formation of the lower layer wiring, the probability is extremely low that a particle is attached again, to the upper layer wiring at the time of formation of the upper layer wiring, at a position corresponding to the nearly disconnected part of the lower layer wiring. Moreover, the lower layer wiring and the upper layer wiring are electrically connected to each other.

Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.

Abstract: The present invention is to provide a chip type electronic part without the risk of generating a tombstone at the time of soldering on a circuit substrate. External electrodes are formed at both end parts of an electronic part element, with the external electrodes comprising electrodes at the base layer formed as a thin film and solders at the outermost layer, with the solders at the outermost layer containing Sn and Pb as the main component and 0.1 to 0.4% by weight of Ag.

Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.

Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.