Patents by Inventor Hidenori Egawa
Hidenori Egawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11244883Abstract: A semiconductor device includes a wiring substrate including a first surface, a second surface opposite to the first surface, a first heat dissipation conductive pattern formed on the first surface, a second heat dissipation conductive pattern formed on the first surface, a first wiring formed on the first surface, and a second wiring formed on the first surface. The semiconductor device also includes a semiconductor chip disposed on the wiring substrate and including a third surface and a fourth surface opposite to the third surface. In plan view, the second wiring is adjacent to the first and second heat dissipation conductive patterns without intervening any wiring and any conductive pattern between the second wiring and the first and second heat dissipation conductive patterns.Type: GrantFiled: October 31, 2019Date of Patent: February 8, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hidenori Egawa
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Publication number: 20200066611Abstract: A semiconductor device includes a wiring substrate including a first surface, a second surface opposite to the first surface, a first heat dissipation conductive pattern formed on the first surface, a second heat dissipation conductive pattern formed on the first surface, a first wiring formed on the first surface, and a second wiring formed on the first surface. The semiconductor device also includes a semiconductor chip disposed on the wiring substrate and including a third surface and a fourth surface opposite to the third surface. In plan view, the second wiring is adjacent to the first and second heat dissipation conductive patterns without intervening any wiring and any conductive pattern between the second wiring and the first and second heat dissipation conductive patterns.Type: ApplicationFiled: October 31, 2019Publication date: February 27, 2020Inventor: Hidenori EGAWA
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Publication number: 20150123274Abstract: A semiconductor device includes a substantially rectangular semiconductor chip having an obverse surface, a first long side, a second long side opposite the first long side, a first short side and a second short side, and a plurality of bump electrodes. A wiring substrate has a main surface, a first side disposed outside of the semiconductor chip and extending substantially parallel with the first long side, a second side disposed outside of the semiconductor chip and extending substantially parallel with the second long side, and a plurality of wiring groups, each including a plurality of wirings. A semiconductor chip is mounted on the wiring substrate such that the obverse surface of the semiconductor chip is faced to the main surface of the wiring substrate and the first long side is located between the first side of the wiring substrate and the second long side, in a plan view.Type: ApplicationFiled: January 14, 2015Publication date: May 7, 2015Inventor: Hidenori EGAWA
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Patent number: 8975762Abstract: A semiconductor device includes a substantially rectangular semiconductor chip having an obverse surface, a first long side, a second long side opposite the first long side, a first short side and a second short side, and a plurality of bump electrodes. A wiring substrate has a main surface, a first side disposed outside of the semiconductor chip and extending substantially parallel with the first long side, a second side disposed outside of the semiconductor chip and extending substantially parallel with the second long side, and a plurality of wiring groups, each including a plurality of wirings. A semiconductor chip is mounted on the wiring substrate such that the obverse surface of the semiconductor chip is faced to the main surface of the wiring substrate and the first long side is located between the first side of the wiring substrate and the second long side, in a plan view.Type: GrantFiled: February 21, 2014Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventor: Hidenori Egawa
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Publication number: 20140167258Abstract: A semiconductor device includes a substantially rectangular semiconductor chip having an obverse surface, a first long side, a second long side opposite the first long side, a first short side and a second short side, and a plurality of bump electrodes. A wiring substrate has a main surface, a first side disposed outside of the semiconductor chip and extending substantially parallel with the first long side, a second side disposed outside of the semiconductor chip and extending substantially parallel with the second long side, and a plurality of wiring groups, each including a plurality of wirings. A semiconductor chip is mounted on the wiring substrate such that the obverse surface of the semiconductor chip is faced to the main surface of the wiring substrate and the first long side is located between the first side of the wiring substrate and the second long side, in a plan view.Type: ApplicationFiled: February 21, 2014Publication date: June 19, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hidenori EGAWA
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Patent number: 8686574Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.Type: GrantFiled: February 8, 2013Date of Patent: April 1, 2014Assignee: Renesas Electronics CorporationInventor: Hidenori Egawa
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Patent number: 8384230Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.Type: GrantFiled: June 2, 2010Date of Patent: February 26, 2013Assignee: Renesas Electronics CorporationInventor: Hidenori Egawa
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Publication number: 20110012265Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.Type: ApplicationFiled: June 2, 2010Publication date: January 20, 2011Applicant: NEC Electronics CorporationInventor: Hidenori Egawa
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Patent number: 5821604Abstract: A hybrid integrated circuit device is equipped with a shield structure, and the shield structure has a peripheral shield frame soldered to a peripheral shield member of a mother board so as to encircle electrodes of the hybrid integrated circuit device therewith, thereby decreasing noise due to the electromagnetic wave generated by the electrodes.Type: GrantFiled: March 8, 1996Date of Patent: October 13, 1998Assignee: NEC CorporationInventor: Hidenori Egawa
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Patent number: 5668406Abstract: Disclosed herein is a semiconductor device having shielded structure of an integrated circuit for improving the noise shielding characteristic. The semiconductor device comprises a wiring substrate 100, a recess 101 formed on one main surface of the wiring substrate 100, an IC chip 12 mounted on the recess 101, a resin 13 formed to cover the IC chip 12 and fill the recess 101, a conductive paste 14 formed on the resin 13, a GND pattern 18 formed on the other main surface of the wiring substrate 100, and a through hole 15 formed in the wiring substrate 100 for connecting the GND pattern 18 to the conductive paste 14 electrically.Type: GrantFiled: December 17, 1996Date of Patent: September 16, 1997Assignee: NEC CorporationInventor: Hidenori Egawa