Abstract: A current sensor includes a first current pathway, a first magnetic sensor arranged near the first current pathway, a second magnetic sensor arranged opposite the first magnetic sensor with the first current pathway in between, a second current pathway, a third magnetic sensor arranged near the second current pathway, a fourth magnetic sensor arranged opposite the third magnetic sensor with the second current pathway in between, and a signal processor that generates a signal based on a quantity of the first measured current from output of the first magnetic sensor and output of the second magnetic sensor, and also generates a signal based on a quantity of the second measured current from output of the third magnetic sensor and output of the fourth magnetic sensor.

Abstract: A current sensor includes a first current pathway, a first magnetic sensor arranged near the first current pathway, a second magnetic sensor arranged opposite the first magnetic sensor with the first current pathway in between, a second current pathway, a third magnetic sensor arranged near the second current pathway, a fourth magnetic sensor arranged opposite the third magnetic sensor with the second current pathway in between, and a signal processor that generates a signal based on a quantity of the first measured current from output of the first magnetic sensor and output of the second magnetic sensor, and also generates a signal based on a quantity of the second measured current from output of the third magnetic sensor and output of the fourth magnetic sensor.

Abstract: A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer.

Abstract: A package substrate has wires that electrically connect to a semiconductor chip, and surface side terminals that are solid and cylindrical and ends of which are electrically connected to the wires. The semiconductor chip is sealed by a sealing resin layer that is formed by molding a sealing resin so as to cover the semiconductor chip. A surface of the sealing resin layer is made to have a height that is the same as that of end surfaces of other ends of the surface side terminals by grinding. Thus, the surface of the sealing resin layer is a ground surface that is a rough surface and is formed by grinding. The end surfaces of the surface side terminals are exposed at the ground surface of the sealing resin layer.

Abstract: A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer.

Abstract: A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer.

Abstract: A semiconductor device includes: a package substrate that includes a recessed portion, with electrode pads that are electrically connected to electrodes of the semiconductor chip being formed inside the recessed portion; a semiconductor chip that is housed in the recessed portion; terminal-use wires that are formed on the surface of the package substrate and are electrically connected to the electrode pads; external connection pads that are formed on a back surface of the package substrate and are electrically connected to the electrode pads; a sealing resin portion that includes a grinded surface that is parallel to the surface of the package substrate, and seals at least the semiconductor chip by a sealing resin; rewiring pads that are formed on the grinded surface; and connecting wires that are formed on the grinded surface and electrically interconnect the terminal-use wires and the rewiring pads.

Abstract: A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer.

Abstract: A semiconductor device includes: a package substrate that includes a recessed portion, with electrode pads that are electrically connected to electrodes of the semiconductor chip being formed inside the recessed portion; a semiconductor chip that is housed in the recessed portion; terminal-use wires that are formed on the surface of the package substrate and are electrically connected to the electrode pads; external connection pads that are formed on a back surface of the package substrate and are electrically connected to the electrode pads; a sealing resin portion that includes a grinded surface that is parallel to the surface of the package substrate, and seals at least the semiconductor chip by a sealing resin; rewiring pads that are formed on the grinded surface; and connecting wires that are formed on the grinded surface and electrically interconnect the terminal-use wires and the rewiring pads.

Abstract: A package substrate has wires that electrically connect a semiconductor chip, and surface side terminals that are solid cylindrical and whose one ends are electrically connected to the wires. The semiconductor chip is sealed by a sealing resin. A surface of the sealing resin is made to be a same height (a same surface) as end surfaces of other ends of the surface side terminals, by grinding, from a surface, a resin layer that is formed by molding so as to cover the semiconductor chip. The surface of the sealing resin is a ground surface formed by grinding. The end surfaces of the surface side terminals are exposed at the ground surface of the sealing resin.

Abstract: A method of manufacturing a semiconductor device which can solve a problem in which a wafer is warped by the influence of thermal contraction of a sealing resin due to a difference in thermal contraction between the wafer and the sealing resin. A second wafer on which electrodes are formed is stacked on a first wafer such that the electrodes of the second wafer are electrically connected to the electrodes formed on the first wafer, a portion between the first wafer and the second wafer is sealed with a resin, the second wafer and the sealing resin are half cut to expose the conductive posts from the sealing resin, conductive bumps for performing electric connection to an external circuit are formed on the exposed conductive posts, and the wafer is diced into independent semiconductor devices.

Abstract: An efficient fabrication method of a SON type semiconductor device is to be provided. A plurality of linear leadframes is arranged side by side separately from each other. A plurality of semiconductor chips with a plurality of electrode pads is mounted over the plurality of the linear leadframes separately. The plurality of the electrode pads is joined to the plurality of linear leadframes with bonding wires. An encapsulation part for encapsulating the semiconductor chip and the bonding wires and an interframe encapsulation part for filling a space between the linear leadframes exposed outside the encapsulation part are formed. A groove part for cutting all the linear leadframes placed right under the semiconductor chip in the orthogonal direction with respect to the direction of extension of the linear leadframes is formed. The leadframes and the interframe encapsulation parts exposed between the plurality of semiconductor chips are cut to be separated into a semiconductor device.

Abstract: A method of manufacturing a semiconductor device which can solve a problem in which a wafer is warped by the influence of thermal contraction of a sealing resin due to a difference in thermal contraction between the wafer and the sealing resin. A second wafer on which electrodes are formed is stacked on a first wafer such that the electrodes of the second wafer are electrically connected to the electrodes formed on the first wafer, a portion between the first wafer and the second wafer is sealed with a resin, the second wafer and the sealing resin are half cut to expose the conductive posts from the sealing resin, conductive bumps for performing electric connection to an external circuit are formed on the exposed conductive posts, and the wafer is diced into independent semiconductor devices.

Abstract: An efficient fabrication method of a SON type semiconductor device is to be provided. A plurality of linear leadframes is arranged side by side separately from each other. A plurality of semiconductor chips with a plurality of electrode pads is mounted over the plurality of the linear leadframes separately in the direction of extending the linear leadframes. The plurality of the electrode pads is joined to the plurality of the linear leadframes with bonding wires. An encapsulation part for encapsulating the semiconductor chip and the bonding wires and an interframe encapsulation part for burying a space between the linear leadframes exposed outside the encapsulation part are formed. A groove part for cutting all the linear leadframes placed right under the semiconductor chip in the vertical direction to the direction of extending the linear leadframes is formed.

Abstract: A method of manufacturing a semiconductor device which can solve a problem in which a wafer is warped by the influence of thermal contraction of a sealing resin due to a difference in thermal contraction between the wafer and the sealing resin. A second wafer on which electrodes are formed is stacked on a first wafer such that the electrodes of the second wafer are electrically connected to the electrodes formed on the first wafer, a portion between the first wafer and the second wafer is sealed with a resin, the second wafer and the sealing resin are half cut to expose the conductive posts from the sealing resin, conductive bumps for performing electric connection to an external circuit are formed on the exposed conductive posts, and the wafer is diced into independent semiconductor devices.

Abstract: A mounting substrate includes a substrate body having at least first and second adjacent chip mounting regions on a surface thereof, and a dicing line between the first and second mounting regions; a first plurality of inner electrodes aligned along a first side of the first chip mounting region; a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region; and an interconnect wiring pattern located between the first and second chip mounting regions, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connecting wiring portions and at least some of the wiring pattern extends obliquely across the dicing line.

Abstract: A slit structure of an encoder for preventing the position precision at high speed operation from deteriorating.

Abstract: A method of manufacturing a semiconductor device which can solve a problem in which a wafer is warped by the influence of thermal contraction of a sealing resin due to a difference in thermal contraction between the wafer and the sealing resin. A second wafer on which electrodes are formed is stacked on a first wafer such that the electrodes of the second wafer are electrically connected to the electrodes formed on the first wafer, a portion between the first wafer and the second wafer is sealed with a resin, the second wafer and the sealing resin are half cut to expose the conductive posts from the sealing resin, conductive bumps for performing electric connection to an external circuit are formed on the exposed conductive posts, and the wafer is diced into independent semiconductor devices.

Abstract: A mounting substrate includes a substrate body having at least first and second adjacent chip mounting regions on a surface thereof, and a dicing line between the first and second mounting regions; a first plurality of inner electrodes aligned along a first side of the first chip mounting region; a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region; and an interconnect wiring pattern located between the first and second chip mounting regions, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connecting wiring portions and at least some of the wiring pattern extends obliquely across the dicing line.

Abstract: A mounting substrate includes a substrate body having at least first and second adjacent chip mounting regions defined on a surface thereof, and further having a dicing line defined between the first and second mounting regions; a first plurality of inner electrodes aligned along a first side of the first chip mounting region, a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region, an interconnect wiring pattern located between the first and second chip mounting region, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connected wiring portions , and wherein at least some of said wiring pattern extend obliquely across the dicing line.