Patents by Inventor Hidenori Hirano

Hidenori Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6586319
    Abstract: A method of fabricating a semiconductor device includes the steps of forming an insulation film on a compound semiconductor layer, forming an opening in the insulation film so as to expose a part of the compound semiconductor layer, forming a gate electrode of a refractory metal compound on the insulation film such that the gate electrode contacts with the compound semiconductor layer at the contact hole, and removing the insulation film by a wet etching process, wherein the wet etching process is conducted by an etchant to which both of the gate electrode and the compound semiconductor layer show a resistance.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: July 1, 2003
    Assignee: Fujitsu Limited
    Inventor: Hidenori Hirano
  • Patent number: 5939737
    Abstract: A method of fabricating a semiconductor device includes the steps of forming an insulation film on a compound semiconductor layer, forming an opening in the insulation film so as to expose a part of the compound semiconductor layer, forming a gate electrode of a refractory metal compound on the insulation film such that the gate electrode contacts with the compound semiconductor layer at the contact hole, and removing the insulation film by a wet etching process, wherein the wet etching process is conducted by an etchant to which both of the gate electrode and the compound semiconductor layer show a resistance.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: August 17, 1999
    Assignee: Fujitsu Limited
    Inventor: Hidenori Hirano
  • Patent number: 5445979
    Abstract: A semiconductor device comprises an active layer formed of a compound semiconductor for allowing carriers travel therethrough for exhibiting a function of the device, a protection layer including a non-doped compound semiconductor layer formed on the active layer, a pair of contact holes formed in the protection layer to expose the active layer, and an electrode filling the contact holes and covering the exposed active layer and extending on the protection layer. Generation of notch can be prevented even upon formation of a contact hole in the non-doped compound semiconductor layer and depositing electrode layer thereon.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: August 29, 1995
    Assignee: Fujitsu Limited
    Inventor: Hidenori Hirano