Abstract: A packet processing apparatus includes a packet buffer unit that temporarily holds packet data, a packet processing unit that processes packet data output from the packet buffer unit, a clock supply unit that supplies a clock signal to the packet processing unit, and a control unit that detects a buffer vacant time indicating a time during which no packet data exists in the packet buffer unit based on an accumulation amount of the packet data in the packet buffer unit, and controls an operational state of the clock supply unit in accordance with the buffer vacant time.

Abstract: In a packet processing device capable of reducing power consumption when time intervals between input packets is increased and an input traffic capacity is reduced, packet processors, N in number (N is an integer of one or more), sequentially perform processing in response to an input packet to output a processed packet and processor packet detectors detect whether or not a packet exists in the packet processors. Responsive to a result of the processor packet detectors, a power supply switch unit controls power supply to the packet processors. Thus, each of the packet processors is intermittently put into an active state by intermittent power supply.

Abstract: A circuit includes: an input buffer for storing input data; a plurality of processing sections connected in series including a head processing section and a tail-end processing section to sequentially process the input data; and a power supply controller for controlling power supply to each of the plurality of processing sections depending on a lapse of time during which no input data is stored in the input buffer.

Abstract: An apparatus for processing a packet includes a packet processor operating in accordance with a clock signal having a predetermined frequency, to process a packet, and a clock-signal generator producing the clock signal and transmitting the clock signal to the packet processor, wherein the clock-signal generator generates a clock signal having a frequency defined in accordance with a time interval at which packets are input into the apparatus.

Abstract: A packet processor having one or two or more packet processing units is provided with a packet detector which detects whether or not a packet exists in a packet processing unit, and outputs a packet detection signal indicating a result of the detection, and a clock frequency controller which controls a clock to be supplied to the packet processing unit based on the packet detection signal.

Abstract: A packet processor having one or two or more packet processing units is provided with a packet detector which detects whether or not a packet exists in a packet processing unit, and outputs a packet detection signal indicating a result of the detection, and a clock frequency controller which controls a clock to be supplied to the packet processing unit based on the packet detection signal.

Abstract: A circuit includes: an input buffer for storing input data; a plurality of processing sections connected in series including a head processing section and a tail-end processing section to sequentially process the input data; and a power supply controller for controlling power supply to each of the plurality of processing sections depending on a lapse of time during which no input data is stored in the input buffer.

Abstract: A packet processing apparatus includes a packet buffer unit that temporarily holds packet data, a packet processing unit that processes packet data output from the packet buffer unit, a clock supply unit that supplies a clock signal to the packet processing unit, and a control unit that detects a buffer vacant time indicating a time during which no packet data exists in the packet buffer unit based on an accumulation amount of the packet data in the packet buffer unit, and controls an operational state of the clock supply unit in accordance with the buffer vacant time.

Abstract: In a packet processing device capable of reducing power consumption when time intervals between input packets is increased and an input traffic capacity is reduced, packet processors, N in number (N is an integer of one or more), sequentially perform processing in response to an input packet to output a processed packet and processor packet detectors detect whether or not a packet exists in the packet processors. Responsive to a result of the processor packet detectors, a power supply switch unit controls power supply to the packet processors. Thus, each of the packet processors is intermittently put into an active state by intermittent power supply.

Abstract: An apparatus for processing a packet includes a packet processor operating in accordance with a clock signal having a predetermined frequency, to process a packet, and a clock-signal generator producing the clock signal and transmitting the clock signal to the packet processor, wherein the clock-signal generator generates a clock signal having a frequency defined in accordance with a time interval at which packets are input into the apparatus.