Patents by Inventor Hidenori Kouketsu

Hidenori Kouketsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741648
    Abstract: A manufacturing yield and reliability of a semiconductor device including a power semiconductor element is improved. A plurality of trenches DT extending in an x direction and spaced apart from each other in a y direction orthogonal to the x direction are formed in a substrate having a main crystal surface tilted with respect to a <11-20> direction. Also, a super-junction structure is constituted of a p-type column region PC made of a semiconductor layer embedded in the trench DT and an n-type column region NC made of a part of the substrate between the trenches DT adjacent in the y direction, and an angle error between the extending direction of the trench DT (x direction) and the <11-20> direction is within ±?. The ? is determined by {arctan {k× (w/h)}}/13 for the trench having a height of h and a width of w. Herein, the k is at least smaller than 2, preferably 0.9 or less, more preferably 0.5 or less, and still more preferably 0.3 or less.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 11, 2020
    Assignees: National Institute of Advanced Industrial Science and Technology, Hitachi, Ltd, Fuji Electric Co., Ltd, Mitsubishi Electric Corporation
    Inventors: Ryoji Kosugi, Shiyang Ji, Kazuhiro Mochizuki, Yasuyuki Kawada, Hidenori Kouketsu
  • Publication number: 20190157399
    Abstract: A manufacturing yield and reliability of a semiconductor device including a power semiconductor element is improved. A plurality of trenches DT extending in an x direction and spaced apart from each other in a y direction orthogonal to the x direction are formed in a substrate having a main crystal surface tilted with respect to a <11-20> direction. Also, a super-junction structure is constituted of a p-type column region PC made of a semiconductor layer embedded in the trench DT and an n-type column region NC made of a part of the substrate between the trenches DT adjacent in the y direction, and an angle error between the extending direction of the trench DT (x direction) and the <11-20> direction is within ±?. The ? is determined by {arctan {k× (w/h)}}/13 for the trench having a height of h and a width of w. Herein, the k is at least smaller than 2, preferably 0.9 or less, more preferably 0.5 or less, and still more preferably 0.3 or less.
    Type: Application
    Filed: June 2, 2017
    Publication date: May 23, 2019
    Inventors: Ryoji Kosugi, Shiyang Ji, Kazuhiro Mochizuki, Yasuyuki Kawda, Hidenori Kouketsu