Abstract: An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N+ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N+ emitter layer (206). Furthermore, the ladder-like N+ emitter layer (206) is formed adjacent to the trench (207), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.

Abstract: An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N+ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N+ emitter layer (206). Furthermore, the ladder-like N+ emitter layer (206) is formed adjacent to the trench (7), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.

Abstract: An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N.sup.+ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N.sup.+ emitter layer (206). Furthermore, the ladder-like N.sup.+ emitter layer (206) is formed adjacent to the trench (207), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.

Abstract: A trench is formed on a main surface of a p+ type monocrystalline silicon substrate. A silicon oxide film is formed extending from the inner surface of trench onto the main surface of p+ type monocrystalline silicon substrate. The thickness of a corner portion positioned on the upper end corner portion of the sidewall of trench in silicon oxide film is larger than the thickness of silicon oxide film positioned on the sidewall of trench. An n type polycrystalline silicon layer extending from the inside of trench onto the main surface of p+ type monocrystalline silicon substrate is formed on silicon oxide film. Thus, a semiconductor device having a trench structure with an improved breakdown voltage for an insulating layer positioned on an upper end corner portion of the sidewall of a trench is obtained.

Abstract: A trench is formed on a main surface of a p+ type monocrystalline silicon substrate. A silicon oxide film is formed extending from the inner surface of trench onto the main surface of p+ type monocrystalline silicon substrate. The thickness of a corner portion positioned on the upper end corner portion of the sidewall of trench in silicon oxide film is larger than the thickness of silicon oxide film positioned on the sidewall of trench. An n type polycrystalline silicon layer extending from the inside of trench onto the main surface of p+ type monocrystalline silicon substrate is formed on silicon oxide film. Thus, a semiconductor device having a trench structure with an improved breakdown voltage for an insulating layer positioned on an upper end corner portion of the sidewall of a trench is obtained.

Abstract: A semiconductor laser device submount disposed between a semiconductor laser chip and a metal block for securing them together includes a metallization structure on each of two opposing surfaces of an Sb-doped submount body. The metallization includes a first Au layer on the surface of the body, an AuSb layer on the first Au layer, and a second Au layer on the AuSb layer.