Patents by Inventor Hidenori Ogata

Hidenori Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130016296
    Abstract: The present invention includes: a reflective electrode (2); a translucent electrode (10); an organic EL layer (21) for emitting blue light, the organic EL layer being sandwiched between the reflective electrode and the translucent electrode; a red fluorescent substance layer (13) for converting the light from the organic EL layer (21) into red light; a green fluorescent substance layer (14) for converting the light from the organic EL layer (21) into green light; and a blue pixel including a light-distribution-characteristic adjusting layer (15) for adjusting a light distribution characteristic of the light from the organic EL layer (21), the present invention being structured such that the reflective electrode (2) and the translucent electrode (10) produce a microcavity effect.
    Type: Application
    Filed: January 27, 2011
    Publication date: January 17, 2013
    Inventors: Yoshimasa Fujita, Hidenori Ogata, Ken Okamoto, Yuhki Kobayashi, Makoto Yamada, Katsumi Kondoh
  • Publication number: 20120326180
    Abstract: A light-emitting element of the present invention includes (i) a light-emitting layer (109), (ii) an electrode layer (110) being transparent to part of light emitted from the light-emitting layer (109), (iii) color converting layers (113, 114), and (iv) a transparent layer (115). The color converting layers (113, 114) and the transparent layer (115) sandwich the transparent electrode layer (110) with the light-emitting layer (109). The color converting layers (113, 114) and the transparent electrode layer (115) contain particles (116, 117, 118) expressing a surface plasmon phenomenon, respectively.
    Type: Application
    Filed: October 28, 2010
    Publication date: December 27, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Masahito Ohe, Yoshimasa Fujita, Yuhki Kobayashi, Ken Okamoto, Hidenori Ogata, Makoto Yamada
  • Publication number: 20120319569
    Abstract: A display device of the present invention includes a red-light-emitting element (1), a green-light-emitting element (2), and a blue-light-emitting element (3). The red-light-emitting element (1) and the green-light-emitting element (2) each include an organic EL section (20) and a color converting layer (15). The color converting layer (15) has an optical distance that extends from (i) a position of the color converting layer from which position light is emitted to (ii) an extraction surface of the color converting layer, the optical distance being varied between the red-light-emitting element (1) and (2). The blue-light-emitting element (3) may include a film-thickness adjusting layer (19) instead of the color converting layer (15).
    Type: Application
    Filed: October 29, 2010
    Publication date: December 20, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Ken Okamoto, Yoshimasa Fujita, Hidenori Ogata, Yuhki Kobayashi, Makoto Yamada, Katsumi Kondoh
  • Publication number: 20120313512
    Abstract: A plurality of illumination panels (10) are hung by up-and-down cords (3). The up-and-down cords (3) have a function of hanging the illumination panels (10) and a function of supplying electric power to the illumination panels (10). Pulling a rod (7), which is a take-up tool causes the up-and-down cords (3) to be taken up and, at the same time, the bottom rail (4) and the illumination panels (10) are also raised. At this time, the up-and-down cords (3) are taken up into the head box (2). As such, when the bottom rail (4) is raised, the up-and-down cords (3) are taken up without bending. This makes it possible to distribute stress that may otherwise be concentrated locally on the up-and-down cords (3). As a result, the up-and-down cords (3) can be prevented from getting broken due to deterioration caused by concentration of stress on the up-and-down cords (3), which concentration is caused by bending etc. of the up-and-down cords (3).
    Type: Application
    Filed: February 16, 2011
    Publication date: December 13, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Makoto Yamada, Yoshimasa Fujita, Yuhki Kobayashi, Ken Okamoto, Hidenori Ogata
  • Publication number: 20120306359
    Abstract: An organic EL component (1) of the present invention includes a reflective anode (11), an organic light-emitting unit (12), a semitransparent cathode (13), and a color converting layer (15). The color converting layer (15) absorbs light emitted by the organic light-emitting unit (12) and having a first color, and emits converted light having a second color different from the first color. The semitransparent cathode (13) has a film thickness of not less than 20 nm and not greater than 30 nm, and efficiently reflects, toward a light extraction side, light emitted from the color converting layer (15).
    Type: Application
    Filed: October 28, 2010
    Publication date: December 6, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Ken Okamoto, Yoshimasa Fujita, Hidenori Ogata, Yuhki Kobayashi, Makoto Yamada, Katsumi Kondoh
  • Publication number: 20120267619
    Abstract: An organic EL element (1) according to the present invention is such that a positive and negative charge transport layer (30) is interposed between a cathode (20) and an anode (10). The positive and negative charge transport layer (30) is composed of a single host material and has a light-emitting region (33) which is doped with a light-emitting dopant. The positive and negative charge transport layer (30) further has at least one of the following blocking regions: an electron blocking region (32), provided closer to the anode (10) than the light-emitting region (33), having a lowest unoccupied molecular orbital lower than that of the lowest unoccupied molecular orbital of the light-emitting region (33); and a hole blocking region (34), provided closer to the cathode (20) than the light-emitting region (33), having a highest occupied molecular orbital higher than that of the highest occupied molecular orbital of the light-emitting region (33).
    Type: Application
    Filed: December 6, 2010
    Publication date: October 25, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Makoto Yamada, Yoshimasa Fujita, Hidenori Ogata, Yuhki Kobayashi, Ken Okamoto
  • Publication number: 20120268445
    Abstract: Provided are an image display device in which a desired number of panels are combined so that a large light-emitting surface is realized, a panel provided in the image display device, and a method for manufacturing the panel. For this purpose, a panel (11) of the present invention includes a rectangular light-emitting section (13); a substrate (12) having a flat surface (12a?) on which the rectangular light-emitting section (13) is provided and a curved adjacent surface (12b?) that is adjacent to one of edge portions of the flat surface which extend along long sides of the rectangular light-emitting section (13); and a terminal group that is drawn out from a long side of the rectangular light-emitting section (13) and that is disposed in the adjacent surface.
    Type: Application
    Filed: December 2, 2010
    Publication date: October 25, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hidenori Ogata, Yuhki Kobayashi, Makoto Yamada, Ken Okamoto, Yoshimasa Fujita, Katsumi Kondoh
  • Publication number: 20120228596
    Abstract: Panel (11) of the present invention includes substrate (12) having flat surface (12a?) having rectangular display section (13), and adjacent surface (12b?) curved from an edge part of surface (12a?) in the vicinity of a long side of surface (12a?). On surface (12b?), terminals, extending from display section (13) (in the vicinity of the long side), are arranged. Edge parts of surfaces (12a?) of substrates (12) of adjacent panels (11) are combined so that longitudinal directions of light-emitting sections (13) are parallel to each other. Surface (12b?) projects on a back surface side of substrate (12). It is thus possible to provide a light-emitting panel device realizing a large light-emitting surface by combining a desired number of panels, an image display device including the light-emitting panel device, an illumination device including the light-emitting panel device, a panel in the light-emitting panel device, and a method of producing the panel.
    Type: Application
    Filed: May 20, 2010
    Publication date: September 13, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshimasa Fujita, Hidenori Ogata, Ken Okamoto, Yuhki Kobayashi, Makoto Yamada
  • Publication number: 20120181915
    Abstract: In an organic EL illumination device (1), a plurality of organic EL elements (4) are provided between an element substrate (30) and a covering substrate (20). A heat dissipation member (14) which covers surfaces of the organic EL elements (4) is provided in a space formed between the element substrate (30) and the covering substrate (20), between each organic EL element (4).
    Type: Application
    Filed: June 21, 2010
    Publication date: July 19, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Emi Yamamoto, Hidenori Ogata, Yoshimasa Fujita, Makoto Yamada
  • Publication number: 20120126218
    Abstract: An organic electric-field element includes an elongated support base member, a first electrode provided on the support base member, an organic layer provided to cover the first electrode, and a second electrode provided to cover the organic layer. At one end portion of the support base member, a two-layer structure region including the support base member and the first electrode is provided, and a three-layer structure region including the support base member, the first electrode, and the organic layer is provided, extending continuously from the other end of the two-layer structure region. At the other end portion of the support base member, a two-layer structure region including the support base member and the second electrode is provided, and a three-layer structure region including the support base member, the second electrode, and the organic layer is provided, extending continuously from one end of the two-layer structure region.
    Type: Application
    Filed: April 13, 2010
    Publication date: May 24, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hidenori Ogata, Yoshimasa Fujita, Mitsuhiro Koden
  • Publication number: 20120112618
    Abstract: An organic electroluminescence illuminating device (L) has a structure in which an organic electroluminescence element (10) is provided and encapsulated between a pair of substrates (20, 21). A light emitting surface of the organic electroluminescence element (10) has a portion which is not parallel to a light extraction surface of the entire illuminating device.
    Type: Application
    Filed: April 13, 2010
    Publication date: May 10, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hidenori Ogata, Emi Yamamoto, Yoshimasa Fujita
  • Patent number: 7439114
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 21, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Patent number: 7061017
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: June 13, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Publication number: 20050287825
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Application
    Filed: August 18, 2005
    Publication date: December 29, 2005
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi kuwahara
  • Patent number: 6797651
    Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber through a chamber window, thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window and productivity is improved.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: September 28, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Hagino, Kazuhiro Imao, Ken Wakita, Toshio Monzen, Hidenori Ogata, Shiro Nakanishi, Yoshihiro Morimoto
  • Publication number: 20040106246
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Application
    Filed: November 14, 2003
    Publication date: June 3, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Publication number: 20020142567
    Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber (100) through a chamber window (120), thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber 100 a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window (120) and productivity is improved.
    Type: Application
    Filed: February 22, 2002
    Publication date: October 3, 2002
    Inventors: Takashi Hagino, Kazuhiro Imao, Ken Wakita, Toshio Monzen, Hidenori Ogata, Shiro Nakanishi, Yoshihiro Morimoto
  • Patent number: 6274414
    Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: August 14, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
  • Patent number: 6072194
    Abstract: Laser anneal processing of a semiconductor layer is repeated in a number of steps. Grain size is increased using high energy ELA for a first step, and grain sizes are uniformed using ELA with low energy for a later step. As a defective crystallization region occurs in an excessive energy region during the ELA for the first step, in the ELA for the second time, excessive energy is removed and the defective crystallization region is eliminated by reducing the energy to an optimal value, thereby improving the crystallinity of a p-Si layer.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: June 6, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ken Wakita, Hidenori Ogata
  • Patent number: 5960323
    Abstract: Laser anneal processing of a semiconductor layer is repeated in a number of steps. Grain size is increased using high energy ELA for a first step, and grain sizes are uniformed using ELA with low energy for a later step. As a defective crystallization region occurs in an excessive energy region during the ELA for the first step, in the ELA for the second time, excessive energy is removed and the defective crystallization region is eliminated by reducing the energy to an optimal value, thereby improving the crystallinity of a p-Si layer.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: September 28, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ken Wakita, Hidenori Ogata