Patents by Inventor Hidenori Saihara

Hidenori Saihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5963822
    Abstract: According to a method of fabricating a selective epitaxial film, a thin insulating film serving as a mask is formed on the entire surface of a semiconductor substrate having a (100) plane. An opening portion reaching the semiconductor substrate is formed in a desired region of the thin insulating film. An epitaxial film is selectively grown in the opening portion. The semiconductor substrate having the selective epitaxial film formed thereon is annealed at at least a pressure of 1,000 Pa and at least a temperature of 800.degree. C. to fill a gap on the contact surface between the thin insulating film and the selective epitaxial film.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Saihara, Hiroshi Naruse, Hiroyuki Sugaya
  • Patent number: 5926725
    Abstract: In a method of manufacturing a semiconductor device, to form an opening in an insulation film such as a silicon oxide on a semiconductor substrate in a reverse tapered sectional configuration such that no gap is formed between a side surface of an epitaxial growth layer formed in the opening and the opening in the insulation film, the insulation film having the opening is subjected to a thermal process in an atmosphere of non-oxidizing gas including hydrogen elements such as hydrogen, silane or disilane gas. An opening is formed in the insulation film on the semiconductor substrate using isotropic etching. As a result of the above-described thermal process, decomposition of a silicon oxide proceeds from the interface between the insulation film and the semiconductor substrate at a side-wall of the opening to eventually form the opening in a reverse tapered sectional configuration at least in an edge portion thereof.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: July 20, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Saihara, Hiroshi Naruse, Hiroyuki Sugaya, Shizue Hori
  • Patent number: 5909623
    Abstract: A manufacturing method of the present invention comprises the first step of forming an epitaxial base layer in an opening of an element-isolating oxide film on a semiconductor substrate in a non-selection condition, the second step of growing a silicon oxide film on the epitaxial base layer and a base polysilicon layer, and the third step of etching the silicon oxide film to expose the polysilicon layer by the etch-back or the CMP. According to this method, the silicon oxide film is left only on the epitaxial base layer, and the planarization of the device can be attained. The present invention also reduces the resistance of the base electrode by providing silicide to the device.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: June 1, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidenori Saihara
  • Patent number: 5877540
    Abstract: A semiconductor device. A semiconductor substrate has a first conductivity. A first insulating layer is on the semiconductor substrate and has an opening so that a portion of the semiconductor substrate is exposed. A semiconductor layer has a second conductivity on the portion. A region in said semiconductor layer prevents a leakage current caused by a minute defect and faceting.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: March 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Naruse, Hiroyuki Sugaya, Hidenori Saihara, Yoshiro Baba