Abstract: A relay device for dividing a storage device into a plurality of unit areas, assigning an unused unit area from among the plurality of unit areas to received channel-specified data, and performing at least one of adjustment of a transmission timing of the data and conversion of the data by using the assigned unit area, is disclosed. The relay device includes an error detector configured to detect an error where the unit area from which the data is to be read is not specified; and an error control configured to recognize a channel of data stored in the unit area that is not specified due to the error detected by the error detector as a target channel, and to invalidate an assignment of the unit area to the recognized target channel.

Abstract: A relay device for dividing a storage device into a plurality of unit areas, assigning an unused unit area from among the plurality of unit areas to received channel-specified data, and performing at least one of adjustment of a transmission timing of the data and conversion of the data by using the assigned unit area, is disclosed. The relay device includes an error detector configured to detect an error where the unit area from which the data is to be read is not specified; and an error control configured to recognize a channel of data stored in the unit area that is not specified due to the error detected by the error detector as a target channel, and to invalidate an assignment of the unit area to the recognized target channel.

Abstract: A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer.

Abstract: A signal processing circuit for controlling reading of segment data from a buffer in which a plurality of segment data generated by dividing a frame and received via a plurality of switches which direct each of the segment data to a designated destination are stored, comprises: a start detecting unit which detects a starting segment representing the first transmitted segment data to the switch among the segment data received after the buffer has emptied; a transmission time acquiring unit which acquires a transmission time at which the starting segment was transmitted to the switch; and a read timing control unit which determines, based on the transmission time, a read timing for reading the segment data from the buffer.

Abstract: A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.

Abstract: A memory control device that can improve the speed of a memory interface. A packet disassembly section disassembles packet data into segments and detects packet quality information. A memory management section has an address management table and manages a state in which the packet data is stored according to the packet quality information. A segment/request information disassembler disassembles the segments into data by an access unit by which memories can be written/read, and generates write requests and read requests according to the access unit. A memory access controller avoids a bank access to which is prohibited because of a bank constraint, extracts a write request or a read request corresponding to an accessible bank from the write requests or the read requests generated, and gains write/read access to the memories.

Abstract: The invention relates to provide a cross-connect switch and a route monitoring assist apparatus both suitable for a synchronous transfer mode. An object of the invention is to attain cross-connect at a low cost with reliability in a much higher rate group than in the conventional example. To this end, the invention provides a cross-connect switch comprising a multiport storage section having a plurality of read ports randomly accessible and a plurality of write ports to which data of a plurality of channels that are time-division-multiplexed are input individually in parallel; an address storage section for storing addresses to be supplied to the respective read ports; and a controlling section for writing data in units of a plurality of channels by supplying write addresses sequentially to each of the write ports, and for supplying addresses stored in the address storage section to the respective read ports.