Patents by Inventor Hidenori Takeda

Hidenori Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220198103
    Abstract: A modeling system (control device) includes a control unit that controls a modeling means to form each of stacked modeling layers, based on modeling data representing a three-dimensional model object that is a modeling target by use of a plurality of modeling layers, a determination unit that measures and determines whether or not a measured value of a stacked height of the formed modeling layer is within a predetermined range set beforehand and including a stacked height of the modeling layer in the modeling data, and in a case where the formed modeling layer has a lacking part in which the stacked height is not within the predetermined range, a correction unit that performs correction modeling by forming a correction member in the lacking part such that the stacked height is within the predetermined range.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 23, 2022
    Inventors: Hiroki MORI, Akihiro TANAKA, Takahiro TACHIBANA, Yasutaka BANNO, Hidenori TAKEDA, Misaki FUKUYAMA
  • Patent number: 9733200
    Abstract: With an image processing device, a presence/absence of a product defect is judged based on detected-image data obtained by a radiographic device that detects radiation that has passed through a product, which is an inspection subject. With the image processing device, a position of a product feature in the detected-image data is identified based on a shape of the product feature indicated by feature data stored in a storage portion in advance, defect candidates are extracted with reference to the identified product feature in the detected-image data, and the presence/absence of a product defect is judged based on characteristic quantities of product defects indicated by a defect characteristic stored in the storage portion in advance and characteristic quantities of the defect candidates.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: August 15, 2017
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Kiichi Sugimoto, Yosuke Fujitomi, Tsuyoshi Tomita, Atsushi Kiya, Akemi Takano, Hidenori Takeda
  • Patent number: 9685549
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer (1) located over the substrate; a second nitride semiconductor layer (2) located over the first nitride semiconductor layer (1), having a larger band gap than the first nitride semiconductor layer (1), and having a recess (11) penetrating into the first nitride semiconductor layer (1); and a third nitride semiconductor layer (12) continuously covering the second nitride semiconductor layer (2) and the recess (11), and having a larger band gap than the first nitride semiconductor layer (1); a gate electrode (5) located above a portion of the third nitride semiconductor layer (12) over the recess (11); and a first ohmic electrode (4a) and a second ohmic electrode (4b) located on opposite sides of the gate electrode (5).
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: June 20, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideyuki Okita, Yasuhiro Uemoto, Masahiro Hikita, Hidenori Takeda, Takahiro Sato, Akihiko Nishio
  • Patent number: 9293574
    Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type nitride semiconductor layer above the second nitride semiconductor layer; two third nitride semiconductor layers of n-type above the second nitride semiconductor layer and located separately on either side of the p-type nitride semiconductor layer; and a first ohmic electrode above one of the two third nitride semiconductor layers and a second ohmic electrode above the other of the two third nitride semiconductor layers; and a gate electrode above the p-type nitride semiconductor layer. The second nitride semiconductor layer includes, in a region above which neither the p-type nitride semiconductor layer nor the two third nitride semiconductor layers is located, a surface layer including p-type impurities identical to those in the p-type nitride semiconductor layer.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: March 22, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideyuki Okita, Yasuhiro Uemoto, Masahiro Hikita, Akihiko Nishio, Hidenori Takeda, Takahiro Sato
  • Publication number: 20150131779
    Abstract: With an image processing device (20), the presence/absence of a product defect is judged based on detected-image data obtained by a radiographic device that detects radiation that has passed through a product, which is an inspection subject. With the image processing device (20), a position of a product feature in the detected-image data is identified based on a shape of the product feature indicated by feature data stored in a DB storage portion (36) in advance, defect candidates are extracted with reference to the identified product feature in the detected-image data, and the presence/absence of a product defect is judged based on characteristic quantities of product defects indicated by the defect characteristic DB stored in the DB storage portion (36) in advance and characteristic quantities of the defect candidates.
    Type: Application
    Filed: June 7, 2013
    Publication date: May 14, 2015
    Inventors: Kiichi Sugimoto, Yosuke Fujitomi, Tsuyoshi Tomita, Atsushi Kiya, Akemi Takano, Hidenori Takeda
  • Publication number: 20140225161
    Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type nitride semiconductor layer above the second nitride semiconductor layer; two third nitride semiconductor layers of n-type above the second nitride semiconductor layer and located separately on either side of the p-type nitride semiconductor layer; and a first ohmic electrode above one of the two third nitride semiconductor layers and a second ohmic electrode above the other of the two third nitride semiconductor layers; and a gate electrode above the p-type nitride semiconductor layer. The second nitride semiconductor layer includes, in a region above which neither the p-type nitride semiconductor layer nor the two third nitride semiconductor layers is located, a surface layer including p-type impurities identical to those in the p-type nitride semiconductor layer.
    Type: Application
    Filed: April 16, 2014
    Publication date: August 14, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Hideyuki OKITA, Yasuhiro UEMOTO, Masahiro HIKITA, Akihiko NISHIO, Hidenori TAKEDA, Takahiro SATO
  • Publication number: 20140097468
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer (1) located over the substrate; a second nitride semiconductor layer (2) located over the first nitride semiconductor layer (1), having a larger band gap than the first nitride semiconductor layer (1), and having a recess (11) penetrating into the first nitride semiconductor layer (1); and a third nitride semiconductor layer (12) continuously covering the second nitride semiconductor layer (2) and the recess (11), and having a larger band gap than the first nitride semiconductor layer (1); a gate electrode (5) located above a portion of the third nitride semiconductor layer (12) over the recess (11); and a first ohmic electrode (4a) and a second ohmic electrode (4b) located on opposite sides of the gate electrode (5).
    Type: Application
    Filed: December 12, 2013
    Publication date: April 10, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Hideyuki OKITA, Yasuhiro UEMOTO, Masahiro HIKITA, Hidenori TAKEDA, Takahiro SATO, Akihiko NISHIO
  • Patent number: 7285457
    Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: October 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidenori Takeda, Toshiharu Tambo
  • Publication number: 20070184757
    Abstract: The present invention provides a polishing sheet that can secure a flatness of a material to be polished and can improve a polishing efficiency. A polishing pad 1 has a polyurethane sheet 2 made of polyurethane resin. The polyurethane sheet 2 has large cells 3 with a generally triangular sectional configuration rounded along a thickness direction thereof. Polyurethane resin exists in the polyurethane sheet 2 in a partition wall manner and fine foams 4 are formed in the polyurethane resin. Fine particles 5 added during manufacture of the polyurethane sheet 2 exist inside some of the fine foams 4 and the fine particles 5 are separable from the fine foams. By separating off fine particles positioned at a polishing face P by dummy polishing or the like, fine foams which evenly reserve a polishing liquid containing abrasive particles are formed at the polishing face P.
    Type: Application
    Filed: April 9, 2007
    Publication date: August 9, 2007
    Applicant: FUJI SPINNING CO., LTD.
    Inventors: Takahiro KUME, Hidenori TAKEDA
  • Patent number: 7220475
    Abstract: The present invention provides a polishing sheet that can secure a flatness of a material to be polished and can improve a polishing efficiency. A polishing pad 1 has a polyurethane sheet 2 made of polyurethane resin. The polyurethane sheet 2 has large cells 3 with a generally triangular sectional configuration rounded along a thickness direction thereof. Polyurethane resin exists in the polyurethane sheet 2 in a partition wall manner and fine foams 4 are formed in the polyurethane resin. Fine particles 5 added during manufacture of the polyurethane sheet 2 exist inside some of the fine foams 4 and the fine particles 5 are separable from the fine foams. By separating off fine particles positioned at a polishing face P by dummy polishing or the like, fine foams which evenly reserve a polishing liquid containing abrasive particles are formed at the polishing face P.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: May 22, 2007
    Assignee: Fuji Spinning Co., Ltd.
    Inventors: Takahiro Kume, Hidenori Takeda
  • Patent number: 7202515
    Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: April 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidenori Takeda, Toshiharu Tambo
  • Publication number: 20060281275
    Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.
    Type: Application
    Filed: August 21, 2006
    Publication date: December 14, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hidenori Takeda, Toshiharu Tomba
  • Publication number: 20060046411
    Abstract: In the method for manufacturing a heterojunction bipolar transistor, a collector contact layer, a collector layer, a base layer, a base protection layer, an emitter layer, an emitter contact layer, and a WSi layer are sequentially formed on a substrate. A resist pattern is then formed on the WSi layer, and the WSi layer is patterned by using the resist pattern as a mask. Thereafter, the emitter contact layer and the emitter layer are sequentially removed by ICP (Inductively Coupled Plasma) dry etching by using the resist pattern as a mask.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 2, 2006
    Inventors: Hidenori Takeda, Toshiharu Tambo
  • Patent number: 6958970
    Abstract: A disk player which can insert and extract a disk, while a disk is being played, into and out of a compact body. During a movement in which one of disk trays is being moved from a disk standby position to a disk playing position, the disk comes into engagement with a disk playing means supporting mechanism to move the disk playing means in a predetermined direction.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: October 25, 2005
    Assignee: Pioneer Corporation
    Inventors: Tomohiro Mizuno, Ken Okamura, Ryuji Tsukagoshi, Hidenori Takeda, Yusuke Akama
  • Publication number: 20050019011
    Abstract: A information-recording apparatus is provided with: a first programming device that is used for programming the execution of the recording processes of recording to the medium and the other medium; a second programming device that is used for programming the execution of the detection/recording process that uses the other medium entered start time information that indicates the start time for executing the detection/recording process; a calculation device which calculates the end time for the detection/recording process based on the information that is the object of the detection/recording process, and the input start time information; a judgment device which determines, based on end time information that indicates the calculated end time and the entered start time information, whether or not the recording process of recording onto the other medium and the detection/recording process are programmed to be executed at the same time; and an output device which outputs notification information.
    Type: Application
    Filed: July 23, 2004
    Publication date: January 27, 2005
    Inventor: Hidenori Takeda
  • Publication number: 20050019003
    Abstract: An editing apparatus which edits the processes of at least a reproduction/recording process that re-records information that is reproduced from a recording medium to that recording medium itself, or a reproduction/recording process that re-records said reproduced information to other recording medium, is provided with: a judgment device which determines whether or not it is possible to execute said reproduction/recording process based on the recorded state of said information that is approved for at least said recording medium or said other recording medium before executing an editing process of said processes; and an output device which outputs notification information to the outside in order to notify of said judgment results before execution of said editing process.
    Type: Application
    Filed: July 22, 2004
    Publication date: January 27, 2005
    Inventor: Hidenori Takeda
  • Publication number: 20040247852
    Abstract: The present invention provides a polishing sheet that can secure a flatness of a material to be polished and can improve a polishing efficiency. A polishing pad 1 has a polyurethane sheet 2 made of polyurethane resin. The polyurethane sheet 2 has large cells 3 with a generally triangular sectional configuration rounded along a thickness direction thereof. Polyurethane resin exists in the polyurethane sheet 2 in a partition wall manner and fine foams 4 are formed in the polyurethane resin. Fine particles 5 added during manufacture of the polyurethane sheet 2 exist inside some of the fine foams 4 and the fine particles 5 are separable from the fine foams. By separating off fine particles positioned at a polishing face P by dummy polishing or the like, fine foams which evenly reserve a polishing liquid containing abrasive particles are formed at the polishing face P.
    Type: Application
    Filed: August 18, 2003
    Publication date: December 9, 2004
    Applicant: FUJI SPINNING CO., LTD.
    Inventors: Takahiro Kume, Hidenori Takeda