Abstract: A light emission driving device sequentially on a time division basis drives a red light source (200R), a green light source (200G), and a blue light source (200B), to calculate a light emission amount control parameter (PWM(k+1)) for setting the light emission amount for one of the light sources. The following values are used: a detected light emission amount (DET(k)) detected for a previous illumination of the same light source, a predetermined value (REF(k+1)) for comparison to the detected light emission amount (DET(k)), and the light emission amount control parameters (PWM(k)) for a previous illumination of the same light source.

Abstract: A light emission driving device sequentially on a time division basis drives a red light source 200R, a green light source 200G, and a blue light source 200B, to calculate a light emission amount control parameter PWM(k+1) for setting the light emission amount for one of the light sources. The following values are used: a detected light emission amount DET(k) detected for a previous illumination of the same light source, a predetermined value REF(k+1) for comparison to the detected light emission amount DET(k), and the light emission amount control parameters PWM(k) for a previous illumination of the same light source.

Abstract: A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at “L” during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal.

Abstract: A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at “L” during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal.

Abstract: A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line/BL, a second transistor having the drain thereof connected to the bit line/BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.

Abstract: A semiconductor device includes an internal source voltage generating circuit (debooster circuit) provided between an external source voltage EVCC and a ground voltage VSS and for generating an internal source voltage IVCC necessary to drive each of internal circuits in the semiconductor device, a booster circuit provided between the internal source voltage IVCC and the ground voltage VSS, for generating a boosted voltage VBST higher than the internal source voltage IVCC, and a capacitor provided between the boosted voltage VBST and the ground voltage, for stabilizing the boosted voltage VBST. The capacitor comprises a P type semiconductor substrate to which the ground voltage is applied, and an N type well region having therein a P type well region with a memory cell formed therein and to which the internal source voltage IVCC is applied.

Abstract: A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line /BL, a second transistor having the drain thereof connected to the bit line /BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.

Abstract: A memory circuit includes a memory cell array having word lines, bit lines and memory cells, and a word line reset circuit for applying an activation level to a word line that is selected, and for applying a lower level which is lower than a deactivation level to the word line when it is non-selected. The word line reset circuit includes a first driver for applying the activation level to the selected word line during a first selected period, a second driver for applying the deactivation level to the word line during a second select period after the first select period, and a third driver for applying the lower level to the word line during a period other than the first and second select periods.

Abstract: A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line /BL, a second transistor having the drain thereof connected to the bit line /BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.

Abstract: The present invention provides a timing circuit for outputting a signal having an amplified pulse width when a signal having a normal pulse width is inputted thereto, characterized in that when glitch noise whose pulse width is small, is inputted to the timing circuit, a signal having a waveform corresponding to the pulse width thereof is outputted from the timing circuit. The timing circuit comprises a first delay circuit whose input is connected to an input terminal, a first NAND circuit having a first input terminal connected to the first delay circuit and a second input terminal connected to the input terminal, a second delay circuit whose input is connected to the output of the NAND circuit, an inverter whose input is connected to the input terminal, and a second NAND circuit having a first input terminal connected to the output of the second delay circuit and a second input terminal connected to the output of the inverter.

Abstract: A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

Abstract: A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

Abstract: A dynamic random access memory system comprising a memory cell matrix, a row address decoder connected to the memory matrix and a counter for producing internal address signals to refresh the cells of the memory cell matrix. A row address buffer converts the external address signals to row address signals in response to an address buffer enabling signal, and a switching circuit connected to the counter and the row address buffer is selectively switching between the counter and the row address buffer in response to an address switching signal. A decoder circuit connected to the output of the switching circuit decodes selected address signals and provides decoded address signals to the row address decoder.