Patents by Inventor Hidenori Wakayanagi

Hidenori Wakayanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11017949
    Abstract: A multi-layer ceramic capacitor according to an embodiment of the present invention includes a multi-layer, side margins and offset sections. The multi-layer includes internal electrodes and dielectric layers alternately laminated. The side margins are configured of a dielectric and disposed to cover side faces of the multi-layer. The offset sections are made with amorphous areas or gap areas. The offset sections are formed between the internal electrodes and the side margins such that ends at side faces of the internal electrodes are offset from the side faces to an inward direction of the multi-layer.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 25, 2021
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yoichi Kato, Kotaro Mizuno, Yukihiro Konishi, Yasunari Kato, Yosuke Sato, Hidenori Wakayanagi, Joji Kobayashi, Toshimitsu Kogure
  • Publication number: 20170287643
    Abstract: A method of producing a multi-layer ceramic electronic component includes: preparing a multi-layer chip including ceramic layers laminated in a first axis direction, internal electrodes disposed between the ceramic layers, and a side surface on which the internal electrodes are exposed; applying a ceramic paste to the side surface; and pressing the applied ceramic paste toward the side surface to planarize the applied ceramic paste.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 5, 2017
    Inventors: Joji Kobayashi, Toshimitsu Kogure, Yasunari Kato, Hidenori Wakayanagi, Yosuke Sato
  • Publication number: 20160351335
    Abstract: A multi-layer ceramic capacitor according to an embodiment of the present invention includes a multi-layer, side margins and offset sections. The multi-layer includes internal electrodes and dielectric layers alternately laminated. The side margins are configured of a dielectric and disposed to cover side faces of the multi-layer. The offset sections are made with amorphous areas or gap areas. The offset sections are formed between the internal electrodes and the side margins such that ends at side faces of the internal electrodes are offset from the side faces to an inward direction of the multi-layer.
    Type: Application
    Filed: May 27, 2016
    Publication date: December 1, 2016
    Inventors: Yoichi Kato, Kotaro Mizuno, Yukihiro Konishi, Yasunari Kato, Yosuke Sato, Hidenori Wakayanagi, Joji Kobayashi, Toshimitsu Kogure