Abstract: A pulse generation circuit generates an output pulse that is set to its activated level in response to a leading edge of a set pulse. The pulse generation circuit comprises an output stage gate having a first output transistor for having the output pulse to be activated level and a second output transistor for having the output pulse to be deactivated level; a first inverter array, for propagating the set pulse and driving the first output transistor; a second inverter array, for propagating a reset pulse, and for driving the second output transistor. To prevent the trailing edge of the set pulse from being delayed, the pulse generation circuit comprises a reset transistor disposed at an inverter output in the first inverter array, being driven in response to the reset pulse propagating through the second inverter array.

Abstract: A latch circuit to perform high-speed input and output operations by reducing a load of an input circuit or an output circuit of the latch circuit. The latch circuit includes four or more inverters connected in a loop to hold a signal, a plurality of input terminals respectively connected to different nodes, and a plurality of output terminals respectively connected to different nodes. At least one input terminal of the latch circuit is used for normal operation of the latch circuit, and at least one input terminal is used for a test operation of the latch circuit. Further, at least one output terminal of the latch circuit is used for normal operation of the latch circuit, and at least one output terminal is used for a test operation of the latch circuit. The latch circuit reduces the number of circuit elements at a connecting point of an input terminal of the latch circuit or at a connecting point of an output terminal of the latch circuit.

Abstract: A pulse generation circuit generates an output pulse that is set to its activated level in response to a leading edge of a set pulse. The pulse generation circuit comprises an output stage gate having a first output transistor for having the output pulse to be activated level and a second output transistor for having the output pulse to be deactivated level; a first inverter array, for propagating the set pulse and driving the first output transistor; a second inverter array, for propagating a reset pulse, and for driving the second output transistor. To prevent the trailing edge of the set pulse from being delayed, the pulse generation circuit comprises a reset transistor disposed at an inverter output in the first inverter array, being driven in response to the reset pulse propagating through the second inverter array.

Abstract: The present invention is intended to realize reduction of time for supplying the pulse signal to the internal circuit. The setup time for latching (holding) the signal can be eliminated by generating a pulse signal without latching (holding) the input signal. A semiconductor integrated circuit is provided, which has a signal input circuit for receiving an input signal and outputting an address signal as a function of the input signal without holding the output signal. A pulse signal generating circuit is coupled to the signal input circuit for generating a pulse signal based on the output signal and a first clock signal.

Abstract: Provided are first to fourth switch circuits of the same configuration as each other, each connected to complementary bus lines DB and *DB to be precharged to the same potential. In the first switch circuit, switches 11 and 15 are connected between an input data signal line SI1 and the DB and between an input data signal line *SI1 and the *DB, respectively, and dummy switches 31 and 32 are connected between the SI1 and the *DB and between the *SI1 and the DB, respectively. Switches 11 to 18 are selectively on/off controlled by outputs of a decoder 20, whereas dummy switches 31 to 38 are normally off.

Abstract: Provided are first to fourth switch circuits of the same configuration as each other, each connected to complementary bus lines DB and *DB to be precharged to the same potential. In the-first switch circuit, switches 11 and 15 are connected between an input data signal line SI1 and the DB and between an input data signal line *SI1 and the *DB, respectively, and dummy switches 31 and 32 are connected between the SI1 and the *DB and between the *SI1 and the DB, respectively. Switches 11 to 18 are selectively on/off controlled by outputs of a decoder 20, whereas dummy switches 31 to 38 are normally off.

Abstract: The present invention is intended to realize reduction of time for supplying the pulse signal to the internal circuit. The setup time for latching (holding) the signal can be eliminated by generating a pulse signal without latching (holding) the input signal. A semiconductor integrated circuit is provided, which has a signal input circuit for receiving an input signal and outputting an address signal as a function of the input signal without holding the output signal. A pulse signal generating circuit is coupled to the signal input circuit for generating a pulse signal based on the output signal and a first clock signal.

Abstract: The present invention is intended to realize reduction of time for supplying the pulse signal to the internal circuit. The setup time for latching (holding) the signal can be eliminated by generating a pulse signal without latching (holding) the input signal. A semiconductor integrated circuit is provided, which has a signal input circuit for receiving an input signal and outputting an address signal as a function of the input signal without holding the output signal. A pulse signal generating circuit is coupled to the signal input circuit for generating a pulse signal based on the output signal and a first clock signal.

Abstract: The semiconductor integrated circuit is provided with a plurality of sub reset signal generators and a main reset signal generator. The sub reset signal generators respectively generate sub power-on reset signals whose timings differ from each other. The main reset signal generator generates a main power-on reset signal according to at least one from any of the sub power-on reset signals. Therefore, even where the characteristics of elements constituting the semiconductor integrated circuit change due to changes in the manufacturing conditions of the semiconductor integrated circuit, one of the sub power-on reset signals is generated at a normal timing. As a result, the main reset signal generator is able to generate a main power-on reset signal by using a normal sub power-on reset signal. That is, it is possible to constitute a power-on resetting circuit having a wide operation margin, wherein the internal circuits can be initialized without fault.