Patents by Inventor Hideo Asano

Hideo Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6275028
    Abstract: In accordance with the present invention, the initialization for orienting the magnetized directions of the free layers of GMR heads (mounted on the diagonally shaded surface of sliders 14) by an external magnetic field is again executed also for the opposite direction, thereby to increase the yield of the GMR heads. Further, it is determined whether the magnetized direction of the pinned layer of GMR heads can be once reversed to the opposite direction, thereby to select damaged GMR heads at an early stage. Then, by performing a reset while performing a quasi-static test for seeing the read back response of the GMR head after restoring the magnetized direction of the pinned layer to a positive rotation, a safe and efficient reset is executed. The reset can be executed not only by applying only a pulse, but also while providing an external magnetic field in the pinning direction, or only by giving a high magnetic field.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: August 14, 2001
    Assignee: International Business Machines Corporation
    Inventors: Takao Matsui, Tatsuya Endo, Hiroaki Suzuki, Kenji Kuroki, Katsushi Yamaguchi, Hideo Asano
  • Patent number: 6219750
    Abstract: A disk drive and a control method thereof to reduce the number of write operations to a medium while minimizing command overhead time. A disk drive 10 comprises a hard disk controller (HDC) 13, a cache memory 14, and a host interface controller (HIC) 15 with a command queue for retaining a plurality of commands which are cached in cache memory 14. The HIC 15 performs the periphery interface processing by hardware. The disk drive 10 further comprises a local microprocessor unit (MPU) 16 for controlling the overall operation of HDD 10, including operations of HDC 13 and HIC 15. The local MPU 16 instructs the HIC 15 to write data to a medium by write commands cached in the cache memory 14. When local MPU 16 retrieves a command from a plurality of write commands cached in cache memory 14 which is completely overwritten by a command more recently issued, a write operation to the medium is not performed by the retrieved command.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: April 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: Atshushi Kanamaru, Toshio Kakihara, Hideo Asano, Atsushi Tobari
  • Patent number: 6209046
    Abstract: Methods and apparatus are described for a data transfer unit between a storage unit and a host, wherein a slower data transfer rate is established when a predetermined error is detected. In one embodiment the cyclicity of the error occurrence calculated and a wait is inserted between data to avoid transferring data at the calculated cyclicity point of the detected error. Optionally the data transfer unit may return the data transfer rate to the original data transfer rate or state after a predetermined time has elapsed, after a predetermined number of commands have been received, after a predetermined amount of data have been transferred, or by combination of these.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Masahiko Sato, Toshio Kakihara, Atsushi Kanamaru, Hiroshi Oshikawa, Hideo Asano
  • Patent number: 6061805
    Abstract: An error recovery procedure (ERP) in a storage device such as a rotating magnetic hard disk drive is executed to the last step regardless of the established time-out period for an instruction, thereby more reliably recovering from errors. In accordance with one embodiment of the invention, when a disk drive receives a reset instruction from a host during the execution of an ERP, it executes the ERP until the error is recovered, or to the last step without interrupting the ERP. Further, in accordance with another embodiment of the invention, when a disk drive receives a reset instruction during the execution of an ERP, it stops execution of the ERP and holds the number K of the step which was completed immediately before stopping, and when receiving a retry instruction after that, sequentially executes the ERP from the K+1-th error recovery step.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: May 9, 2000
    Assignee: International Business Machines Corporation
    Inventors: Hiroaki Suzuki, Hideo Asano, Atsushi Tobari, Satoshi Nishino, Shuji Yamada, Haruo Andoh, Tsuguaki Kowa
  • Patent number: 5896540
    Abstract: The object is to control an interrupt request to be asserted to a host in all of a prereading mode, a postreading mode, and a both-reading mode. Until the count value of a counter becomes equal to the content of a delay register, the reset state of a flip-flop is held and an IRQ is not asserted to the host. When the read signal of a status register is input through an OR gate to a flip-flop for a period in which the count value of the counter becomes equal to the content of the delay register, the flip-flop is set and the Q output remains held in a logic high state, as the postreading mode or the both-reading mode. When the counter value of the counter becomes equal to the content of the delay register, the output of a comparator will go low and the flip-flop will be reset, so that the IRQ is asserted to the host by a CDR.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: April 20, 1999
    Assignee: International Business Machines Corporation
    Inventors: Hideo Asano, Masayuki Murakaami
  • Patent number: 5872955
    Abstract: To reduce read and write times for data in a disk drive, the data of a file is rearranged into continuous recording areas on a disk. A file has a host-specified address and a physical address. The physical address corresponds to the recording area on a disk where the file is stored. The host-specified and physical addresses are stored in a conversion table. The controller receives the host-specified address and a command for reading the file. Based on the host-specified address, the controller determines the physical address from the conversion table. Based on the physical address, the controller reads the data from the disk and sends the data to the host. Thereafter, the controller examines the physical address in the conversion table to determine if the data is recorded on a physically continuous recording area on the disk. If not, the data is moved to a physically continuous recording area, and the physical address in the conversion table is updated.
    Type: Grant
    Filed: November 28, 1995
    Date of Patent: February 16, 1999
    Assignee: International Business Machines Corporation
    Inventor: Hideo Asano
  • Patent number: 5872671
    Abstract: When a sharp change in signal judged due to thermal asperities has appeared, a disk drive apparatus according to the present invention repeats the unidirectional seek operation in a region centered on the belonging cylinder position of the track in which the read error has occurred as one data recovery operation, then scrubs and removes the thermal asperities by putting the component surface around the MR head into positive contact with the asperities, thereby eliminating the fundamental cause of a read error caused by thermal asperities.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: February 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Hiroaki Suzuki, Akira Kibashi, Yoshio Yamamoto, Hideo Asano
  • Patent number: 5598370
    Abstract: A nonvolatile memory-with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: January 28, 1997
    Assignee: International Business Machines Corporation
    Inventors: Hideto Niijima, Hideo Asano, Yoshinori Sakaue, Takashi Toyooka
  • Patent number: 5572659
    Abstract: An adapter connected between a host computer and disk storage devices provides interfaces for connecting to the host computer and the disk storage devices having the same interface design. The adapter itself includes control means for building a redundant disk storage system. Moreover, the adapter itself includes means for detecting and indicating a failed disk storage device, means for replacing the failed disk storage device, and means for rebuilding a redundant disk storage system after the replacement of disk storage devices. A command is configured so that the host computer can have access to each of disk storage devices for maintenance purposes. The adapter makes it easy to configure a highly reliable redundant disk storage system for a small computer system without any change to existing hardware or software.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: November 5, 1996
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Iwasa, Hideo Asano, Yutaka Shimizu
  • Patent number: 5519882
    Abstract: An object of the present invention is to specify two disk drive apparatuses which are connected to an AT interface as a master or slave HDD for local or cable selection by only one jumper block. A disk drive apparatus connected to data processing means through a plurality of interface lines including one interface line connected to a first voltage level of said data processing means, including:a plurality of connection points connected respectively to said plurality of interface lines,a first connection point capable of being selectively connected to said one interface line,a second connection point kept at a floating voltage,a third connection point tied to the first voltage level,a fourth connection point tied to a second voltage level and selectively connected to one of said first, second, and third connection points, andcontrol means connected to said fourth connection point and recognizes itself as a first or second disk drive apparatus by detecting a voltage level of the fourth connection point.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: May 21, 1996
    Assignee: International Business Machines Corporation
    Inventors: Hideo Asano, Masayuki Murakami, Keisuke Shimomura
  • Patent number: 5511939
    Abstract: A multi-blade fan having a fan assembly including a bottom plate and a plurality of circumferentially spaced blades and a casing for the fan assembly therein having an outlet duct extending therefrom for discharge of the air flows. The fan assembly includes an annular shroud connected to the axial ends of the blades remote from the bottom plate. The casing includes a bottom wall for rotatably connecting the fan assembly, a top wall for defining an air inlet for axially introducing the air into the casing, and a tubular wall connecting the bottom and top walls. The top wall of the casing adjacent to the inlet opening forms an annular projection having a bell cross sectional shape opened inwardly so that an axial end of the shroud extends thereto. The bell cross section portion radially extends to a portion that is inclined downwardly in the outward direction, which faces the shroud so that a small gap extending radially is created.
    Type: Grant
    Filed: July 27, 1994
    Date of Patent: April 30, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Takahiro Tokunaga, Yukio Uemura, Hideo Asano, Hikaru Sugi, Teruhiko Kameoka, Yasushi Kondo
  • Patent number: 5457787
    Abstract: An interface circuit for a peripheral device is disclosed that can accurately cope with any host with the same hardware whether the host is in the pre-read mode or the post-read mode and can send an interrupt request to the host practically without a waiting time if the host is in the post-read mode. The interface circuit generates an interrupt request (IRQ) to a host in response to a data request (DRQ) from a peripheral device (HDD) and drops the interrupt request if the status of the peripheral device is read by the host; it detects that the host operates in a post-read mode, and responds to the post-read mode detect signal and the status reading by the host in order to enable the regeneration of the interrupt request to the host.
    Type: Grant
    Filed: October 4, 1993
    Date of Patent: October 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: Hideo Asano, Masayuki Murakami
  • Patent number: 5457658
    Abstract: A nonvolatile memory with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence number. When erasing a given sector, a controller saves its sequence number prior to erasure. Then, when initializing a given erased sector, the controller sets its sequence number to a value greater than the current maximum sequence number. The controller writes user data to sectors other than the cluster information sector for the cluster thus initialized according to their address sequence. Accordingly, an invalid sector can be distinguished from a valid sector without using an overwrite approach.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: October 10, 1995
    Assignee: International Business Machines Corporation
    Inventors: Hideto Niijima, Hideo Asano, Yoshinori Sakaue, Takashi Toyooka
  • Patent number: 5419680
    Abstract: A multi-blade blower with a reduced operating noise. The blower has a casing 3, inside of which a noise generator of a circular cross sectional shape is arranged at a position adjacent a throat of the scroll passageway. The noise generator has a radial gap S with respect to the outer edge of blade which is the same as a radial gap of the throat with the outer edge of the blade, and the spacing between the throat and the noise generator in the direction of the rotation of the wheel is 1.5 times of the blade pitch of the wheel.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: May 30, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hideo Asano, Yasushi Kondo, Yukio Uemura, Teruhiko Kameoka
  • Patent number: 5406529
    Abstract: A flash-erase memory includes a plurality of blocks accessible by a processor and, in association with each block, a block ID representing an address (RBA) specified by the processor upon writing, a revision code (RC) indicating how many times the processor performed writing using the same RBA, and an erase count (EC) indicating the number of times of erasing of this block are stored. Writing is performed to a writable block having the minimum erase count, and if there is a different block having the same block ID as the address specified by the processor, its revision code is updated and used as a revision code of the written block, and the different block is erased and its erase count is updated.
    Type: Grant
    Filed: September 21, 1993
    Date of Patent: April 11, 1995
    Assignee: International Business Machines Corporation
    Inventor: Hideo Asano
  • Patent number: 5352089
    Abstract: A multi-blade fan having a fan assembly including a bottom plate and a plurality of circumferentially spaced blades and a casing for the fan assembly therein having an outlet duct extending therefrom for discharge of the air flows. The fan assembly includes an annular shroud connected to the axial ends of the blades remote from the bottom plate. The casing includes a bottom wall for rotatably connecting the fan assembly, a top wall for defining an air inlet for axially introducing the air into the casing, and a tubular wall connecting the bottom and top walls. The top wall of the casing adjacent to the inlet opening forms an annular projection having a bell cross sectional shape opened inwardly so that an axial end of the shroud extends thereto. The bell cross section portion radially extends to a portion that is inclined downwardly in the outward direction, which faces the shroud so that a small gap extending radially is created.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: October 4, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventors: Takahiro Tokunaga, Yukio Uemura, Hideo Asano, Hikaru Sugi, Teruhiko Kameoka, Yasushi Kondo
  • Patent number: 5205156
    Abstract: A device for providing a signal warning of a clogging of a dust filter. A pair of air flow speed sensors A and B are arranged downstream of two sections of a dust filter 1 arranged in an air duct 1, and the outputs of the sensors A and B are connected to a comparator 6 having an output connected to a warning device 7. An obstacle 3 is arranged upstream or downstream of one section of the filter 1. When the filter is new, the speed of the air flow detected by the sensor B without an obstacle is higher than that detected by the sensor A located downstream of the obstacle, but the speed of clogging at the section without an obstacle is much higher than that at the section located downstream of the obstacle, and thus, after continuous use, the air speed detected by the sensor B becomes equal to that detected by the sensor A. The values of the detected speeds are compared to determine a degree of clogging of the filter, and to issue a warning signal when needed.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: April 27, 1993
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hideo Asano, Kenichi Fujiwara, Toshihiro Takahara
  • Patent number: 5162020
    Abstract: An air-conditioner has a heater core in an air passage. A bypass passage is formed within the air passage and at a side portion of the heater core. A holding shaft is pivotally disposed at the boundary between an air-flow through the heater core and an air-flow through the bypass passage. A sliding shaft is disposed upstream of the heater core and slides to cross a substantially whole area of the air passage. A first end and second end of a variable length damper which varies its length are connected to the sliding shaft and the holding shaft respectively so that the variable length damper moves in such a manner that its length varies in response to a distance between the sliding shaft and the holding shaft.
    Type: Grant
    Filed: March 29, 1991
    Date of Patent: November 10, 1992
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hideo Asano, Akihito Higashihara, Yasufumi Kojima
  • Patent number: 5145456
    Abstract: An automotive air-conditioner has a casing forming an air passage through which an air passes and a film damper slidably disposed in the casing in such a manner to face to the air passage. The film damper having openings opens and closes the air passage. Holes are disposed on the film damper for indicating a position of the opening: Photointerrupters are disposed on the casing to detect the holes and output a present position signal that shows a present position of the film damper. A mode setting portion outputs a target position signal that shows a target position of the film damper. A microcomputer compares the present position signal with the target position signal, so that the microcomputer controls the film damper to stop at the target position.
    Type: Grant
    Filed: May 28, 1991
    Date of Patent: September 8, 1992
    Assignee: Nippondenso Co., Ltd.
    Inventors: Koichi Ito, Hideo Asano, Akihito Higashihara
  • Patent number: 4748823
    Abstract: A freezer-refrigerator for automotive vehicles, which includes a freezing chamber and a refrigeration chamber. The freezing chamber includes a freezing evaporator and a first cold storage member. The refrigeration chamber includes a refrigeration evaporator and a second cold storage member. Both evaporators are connected in series so that refrigerant flows from a compressor through the freezing evaporator and then through the refrigeration evaporator under a control of a solenoid valve which is controlled by signal from a temperature sensor provided in at least one of the chambers, thus controlling the freezing and refrigeration. The freezing temperature of the second cold storage member is set higher than that of the first cold storage member thereby to maintain the interior of the chambers at a temperature near the freezing temperature of the cold storage members for long time even after the compressor stops.
    Type: Grant
    Filed: December 5, 1985
    Date of Patent: June 7, 1988
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hideo Asano, Kazuhisa Makida, Kenichi Fujiwara, Katsumi Hatanaka