Patents by Inventor Hideo Ikai

Hideo Ikai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8775886
    Abstract: The self-healing system comprises a self-healing processor and an error mitigation system. The self-healing processor includes a code block associated with the operation of a portion of digital logic. The self-healing processor also includes a dynamic signature analysis circuit. The processor executes the code block. The dynamic signature analysis circuit creates a dynamic signature representing the operation of the portion of digital logic associated with the code block. The error mitigation system receives the dynamic signature from the dynamic signature analysis circuit. The error mitigation system compares the dynamic signature to a static signature to determine if the signatures match. If the signatures do not match, then the digital logic associated with the code block has an error. The error mitigation system retries execution of the code block. The error mitigation system stores log information describing the above events.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: July 8, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Roger D. Melen, Nader W. Moussa, Makoto Honda, Hideo Ikai, Kozo Kato
  • Publication number: 20100281134
    Abstract: The self-healing system comprises a self-healing processor and an error mitigation system. The self-healing processor includes a code block associated with the operation of a portion of digital logic. The self-healing processor also includes a dynamic signature analysis circuit. The processor executes the code block. The dynamic signature analysis circuit creates a dynamic signature representing the operation of the portion of digital logic associated with the code block. The error mitigation system receives the dynamic signature from the dynamic signature analysis circuit. The error mitigation system compares the dynamic signature to a static signature to determine if the signatures match. If the signatures do not match, then the digital logic associated with the code block has an error. The error mitigation system retries execution of the code block. The error mitigation system stores log information describing the above events.
    Type: Application
    Filed: March 31, 2009
    Publication date: November 4, 2010
    Inventors: Roger D. Melen, Nader W. Moussa, Makoto Honda, Hideo Ikai, Kozo Kato
  • Patent number: 6025064
    Abstract: A reinforcing plate is overlaid with a decoration sheet with a first adhesive layer interposed, and heated and pressed to form first laminate. A surface of the decoration sheet in the first laminate is coated with a clear second adhesive layer of a liquid polyurethane resin, a surface of which in turn is overlaid with a clear film and heated and pressed to prepare a second laminate. The second laminate is placed within a mold and a resin is insert molded on the reinforcing plate in the second laminate. A clear hard coating is preferably formed on a surface of the second laminate in order to provide higher abrasion resistance.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: February 15, 2000
    Assignees: Toyoda Gosei Co., Ltd., Kosuga & Co., Ltd.
    Inventors: Toshimichi Kawata, Ryoiti Takada, Hideo Hirano, Hideo Ikai