Abstract: A semiconductor memory device is operable in normal and test operation modes. At the test operation, in response to a first active command, a row address signal that is input from the outside is captured in the row decoder, and in response to a first write/read command, a column address signal input from the outside is captured in the column decoder. At this time, a word line and a bit line are not selected. Thereafter, in response to a second active command, a word line corresponding to the row address signal is selected in the row decoder, and, in response to a second write/read command, a bit line that corresponds to the column address signal is selected in the column decoder. The time period from the time at which the second read/write command is input to the time at which the second active command is input, is measured as tRCD.

Abstract: A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.

Abstract: High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b outputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data signal. RAM 11a includes a strobe signal control unit 15a that determines whether RAM 11b connected in parallel with the RAM 11a is in a read state or not, and delays an output start timing of data strobe signal DQS when the RAM 11b is in the read state. Strobe signal control unit 15a of the RAM 11a controls output start timing so that a latter half portion of a preamble period of the data strobe signal DQS to be output coincides with a postamble period of the data strobe signal DQS output by the RAM 11b.

Abstract: A semiconductor memory device is operable in normal and test operation modes. At the test operation, in response to a first active command, a row address signal that is input from the outside is captured in the row decoder, and in response to a first write/read command, a column address signal input from the outside is captured in the column decoder. At this time, a word line and a bit line are not selected. Thereafter, in response to a second active command, a word line corresponding to the row address signal is selected in the row decoder, and, in response to a second write/read command, a bit line that corresponds to the column address signal is selected in the column decoder. The time period from the time at which the second read/write command is input to the time at which the second active command is input, is measured as tRCD.

Abstract: A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.

Abstract: Disclosed is a semiconductor device including chips having output terminals connected in common to an external terminal. Each of the chips includes a data input and output section that provides a difference during testing between a first driving capability setting the output terminal to a first power supply potential side and a second driving capability setting the output terminal to a second power supply potential side. During testing, the second driving capability is set so as to be higher than the first driving capability. The output signal level from each chip to the terminal equal to the second power supply potential indicates a fail, and the output signal level from each chip to the terminal equal to the first power supply potential indicate a pass. Under this condition, if at least one or more of the multiple chips outputs a fail signal, the second power supply potential is delivered to the external terminal to which the terminals are connected in common.

Abstract: A feed screw mechanism including a screwed shaft which moves linearly along with the control shaft, and a rotation spindle which rotates in a circumferential direction. The feed screw mechanism converts a rotational movement of the rotation spindle into a linear movement of the screwed shaft. A protrusion protrudes outwardly from the rotation spindle. An internal thread member engages with an outer wall surface of the rotation spindle. A motor stator generating a magnetic is positioned over the rotation spindle, and is sandwiched between the protrusion and the internal thread member in an axial direction of the rotation spindle.

Abstract: High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b outputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data signal. RAM 11a includes a strobe signal control unit 15a that determines whether RAM 11b connected in parallel with the RAM 11a is in a read state or not, and delays an output start timing of data strobe signal DQS when the RAM 11b is in the read state. Strobe signal control unit 15a of the RAM 11a controls output start timing so that a latter half portion of a preamble period of the data strobe signal DQS to be output coincides with a postamble period of the data strobe signal DQS output by the RAM 11b.

Abstract: An actuator for a valve lift controller comprises a case forming a first and second spaces therein. The first space is supplied with lubricating fluid. The actuator further comprises a feed screw mechanism including a cylindrical spindle and a screw, and converts a rotational movement of the spindle to a linear movement of the screw. The spindle includes a first end portion open to the first space and a second end portion closed to the second space therein. The screw straddles borders between an interior of the spindle, the first space, and an external space. The actuator includes a motor unit which is located in the second space and rotates the spindle. The actuator further includes a sealing member sealing a gap between the case and the spindle to separate the first and second spaces.

Abstract: An actuator for a valve lift controller linearly driving a control shaft of a changing mechanism comprises a feed screw mechanism including a screwed shaft linearly moving along with the control shaft, and a rotation spindle rotating coaxially with the screwed shaft. The feed screw mechanism converts a rotational movement of the rotation spindle into a linear movement of the screwed shaft. Moreover, the actuator comprises a unit attached to the rotation spindle, an electric power distributor located at an opposite side of the screw mechanism relative to the changing mechanism, and an stopper member restricting a movement of the unit in the axial direction from an electric power distributor to the unit.

Abstract: Described herein is a desiccant air-conditioning system which is characterized in that the system is equipped with an introducing route where process air is introduced into a geothermal heat exchanger, a supplying route where the process air which is cooled by the geothermal heat exchanger is introduced into a space to be air-conditioned and a desiccant wheel which is placed in an extending manner over both of the introducing route and the supplying route and, when the desiccant wheel is rotated so that each part thereof is successively positioned to said introducing route and supplying route, the process air after cooling is dehumidified by said desiccant wheel and the desiccant wheel is regenerated by the process air before cooling.

Abstract: A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal.

Abstract: A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.

Abstract: A feed screw mechanism including a screwed shaft which moves linearly along with the control shaft, and a rotation spindle which rotates in a circumferential direction. The feed screw mechanism converts a rotational movement of the rotation spindle into a linear movement of the screwed shaft. A protrusion protrudes outwardly from the rotation spindle. An internal thread member engages with an outer wall surface of the rotation spindle. A motor stator generating a magnetic is positioned over the rotation spindle, and is sandwiched between the protrusion and the internal thread member in an axial direction of the rotation spindle.

Abstract: An actuator for a valve lift control device linearly moves a control shaft to change a valve lift in accordance with an axial position of the control shaft. A first and a second rotation cam integrally rotate around a common rotation axis by transmission of torque, so that a direct acting follower, which includes a first and a contact members, linearly moves with a control shaft. The first and a second rotation cams are respectively in contact with the first and the second contact members via a first and a second contact points. The first contact point is located on the opposite side of the second contact point with respect to the rotation axis. A sum of a first rotation cam lift of the first rotation cam and a second rotation cam lift of the second rotation cam is substantially constant in a predetermined rotation angular range of the first rotation cam and the second rotation cam.

Abstract: A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

Abstract: An actuator for a valve lift controller comprises a case forming a first and second spaces therein. The first space is supplied with lubricating fluid. The actuator further comprises a feed screw mechanism including a cylindrical spindle and a screw, and converts a rotational movement of the spindle to a linear movement of the screw. The spindle includes a first end portion open to the first space and a second end portion closed to the second space therein. The screw straddles borders between an interior of the spindle, the first space, and an external space. The actuator includes a motor unit which is located in the second space and rotates the spindle. The actuator further includes a sealing member sealing a gap between the case and the spindle to separate the first and second spaces.

Abstract: An actuator for a valve lift controller linearly driving a control shaft of a changing mechanism comprises a feed screw mechanism including a screwed shaft linearly moving along with the control shaft, and a rotation spindle rotating coaxially with the screwed shaft. The feed screw mechanism converts a rotational movement of the rotation spindle into a linear movement of the screwed shaft. Moreover, the actuator comprises a unit attached to the rotation spindle, an electric power distributor located at an opposite side of the screw mechanism relative to the changing mechanism, and an stopper member restricting a movement of the unit in the axial direction from an electric power distributor to the unit.

Abstract: The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.

Abstract: The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array 30. Then, a test signal TE1 is set “1” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit 51. A first address for test is applied to an address terminal 21, whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal 21, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array 30 are checked to decide the presence or absence of any abnormality.