Patents by Inventor Hideo Isogai
Hideo Isogai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9430310Abstract: A watchdog timer including a first register that stores a first overflow time, a second register that stores a second overflow time, a detector and a counter that continues to count a clock signal to the first overflow time. When the detector detects an execution of a program for a flash memory, the counter clears a count value and continues to count the clock signal to the second overflow time.Type: GrantFiled: November 28, 2014Date of Patent: August 30, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hideo Isogai
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Publication number: 20150089307Abstract: A watchdog timer including a first register that stores a first overflow time, a second register that stores a second overflow time, a detector and a counter that continues to count a clock signal to the first overflow time. When the detector detects an execution of a program for a flash memory, the counter clears a count value and continues to count the clock signal to the second overflow time.Type: ApplicationFiled: November 28, 2014Publication date: March 26, 2015Inventor: Hideo Isogai
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Patent number: 8904222Abstract: A watchdog timer includes an execution address detection section comparing a value of a program counter of a central processing unit with an address of a predetermined area, a timer count section having a first overflow time set thereto when the execution address detection section indicates that the value of the program counter has entered the predetermined area, and a counter clear control section generating a request signal for clearing the timer count section when the execution address detection section indicates that the value of the program counter has exited from the predetermined area.Type: GrantFiled: February 16, 2010Date of Patent: December 2, 2014Assignee: Renesas Electronics CorporationInventor: Hideo Isogai
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Patent number: 7915926Abstract: A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or an internal circuit, and activation control units that control activation of the input circuits or the output circuits that are electrically connected to the pads based on the read access signal, the pads receiving the signals from the external circuit or the internal circuit.Type: GrantFiled: May 3, 2010Date of Patent: March 29, 2011Assignee: Renesas Electronics CorporationInventors: Hideo Isogai, Kentarou Tanaka
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Publication number: 20100283508Abstract: A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or an internal circuit, and activation control units that control activation of the input circuits or the output circuits that are electrically connected to the pads based on the read access signal, the pads receiving the signals from the external circuit or the internal circuit.Type: ApplicationFiled: May 3, 2010Publication date: November 11, 2010Applicant: NEC Electronics CorporationInventors: Hideo ISOGAI, Kentarou Tanaka
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Publication number: 20100211813Abstract: A watchdog timer includes an execution address detection section comparing a value of a program counter of a central processing unit with an address of a predetermined area, a timer count section having a first overflow time set thereto when the execution address detection section indicates that the value of the program counter has entered the predetermined area, and a counter clear control section generating a request signal for clearing the timer count section when the execution address detection section indicates that the value of the program counter has exited from the predetermined area.Type: ApplicationFiled: February 16, 2010Publication date: August 19, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Hideo Isogai
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Patent number: 7710138Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.Type: GrantFiled: January 5, 2009Date of Patent: May 4, 2010Assignee: NEC Electronics CorporationInventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
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Patent number: 7564255Abstract: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer between the first and second latch circuits. The area of the first contact pad is larger than that of the second contact pad.Type: GrantFiled: February 17, 2006Date of Patent: July 21, 2009Assignee: NEC Electronics CorporationInventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
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Patent number: 7557646Abstract: A semiconductor circuit is installed on a printed circuit board having a power wiring pattern and a ground wiring pattern that do not intersect. The semiconductor circuit includes a first power supply terminal and a first ground terminal for a first side of the semiconductor circuit, and a second power supply terminal and a second ground terminal for a second side opposing to the first side. The direction from the first power supply terminal to the first ground terminal is the same as the direction from the second power supply terminal to the second ground terminal.Type: GrantFiled: May 8, 2006Date of Patent: July 7, 2009Assignee: NEC Electronics CorporationInventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
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Publication number: 20090121755Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.Type: ApplicationFiled: January 5, 2009Publication date: May 14, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
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Patent number: 7492036Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.Type: GrantFiled: February 28, 2006Date of Patent: February 17, 2009Assignee: Nec Electronics CorporationInventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
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Patent number: 7463547Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.Type: GrantFiled: January 26, 2006Date of Patent: December 9, 2008Assignee: NEC Electronics CorporationInventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
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Publication number: 20060261451Abstract: A semiconductor circuit is installed on a printed circuit board having a first wiring pattern and a second wiring pattern. The semiconductor circuit includes a first power supply terminal and a first ground terminal which are provided for a first side of the semiconductor circuit. The first power supply terminal is connected with the first wiring pattern. The first ground terminal is connected with the second wiring pattern. A second power supply terminal and a second ground terminal are provided for a second side opposing to the first side. The second power supply terminal is connected with the first wiring pattern and the second ground terminal is connected with the second wiring pattern. The first and second power and ground terminals are arranged such that the first wiring pattern and the second wiring pattern do not intersect in a region of the wiring substrate corresponding to the semiconductor circuit.Type: ApplicationFiled: May 8, 2006Publication date: November 23, 2006Inventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
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Publication number: 20060208345Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.Type: ApplicationFiled: February 28, 2006Publication date: September 21, 2006Inventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou
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Publication number: 20060190779Abstract: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer between the first and second latch circuits. The area of the first contact pad is larger than that of the second contact pad.Type: ApplicationFiled: February 17, 2006Publication date: August 24, 2006Inventors: Shinichi Nakatsu, Hideo Isogai, Takehiro Masumoto, Kazuyuki Nishizawa, Toshihide Tsuboi, Kimiharu Etou