Abstract: In a latch-type address buffer circuit for use in a clock-synchronous CMIS.RAM, a transistor is connected between an inverter, which is supplied with an address signal and the power source. A clock circuit is provided for generating an internal clock signal by which only in the period of latching the input address signal, the transistor is turned ON to make the inverter operative, thus reducing the total power consumption.

Abstract: In a semicondcutor memory device there is provided a specific layout of each element effectively excluding a number of "bridge" crossings for specific lines connecting the elements particularly buffer circuits and a decoder circuit, and thereby reducing the amount of resistance in the lines connecting specific elements, and increasing the signal transmission speed in the specific lines. A control circuit is arranged either beneath or above a portion of the ground line or the electric power line and the control circuit is connected to either of these lines by further vertical lines, thereby eliminating certain bridges.

Abstract: A semiconductor memory circuit having reduced read-access time and comprising a plurality of first and second common line pairs, each including a bit line and a data line connected in series is disclosed. Conventional static RAM memory cells are connected between each of the bit line pairs. A write-control circuit and sense amplifier are connected between each of the data bus pairs. At least one bypassing transistor is connected between each of the first and second common line pairs for conducting current between each of the lines of the common line pairs, thus reducing the read-access time.

Abstract: A photo-electric converting apparatus comprises an array wherein a plurality of photo-electric converting elements are provided, each of which having a semiconductor film layer arranged between an electrode layer and another electrode layer formed on a substrate, and having at least either a rectifying contact or a P-N junction. When the array is irradiated with light under such condition that substantially no bias voltage is applied between the electrode layers of the array, each of the photo-electric converting elements produces forward e.m.f., and forward current flows. A capacitive means in each of the photo-electric converting elements is charged with the forward current, and the capacitive means are discharged successively by scanning pulses, and timed pulse signals are outputted. The present invention discloses further various concrete constructions of the photo-electric converting element and the array thereof with high efficiency of conversion.

Abstract: A decoder for decoding address signals and a clock signal, in a synchronous CMOS memory, comprising an MOS transistor of one conductivity-type, to whose gate is applied a clock-including address signal, and a plurality of MOS transistors of the opposite conductivity-type connected in series, to each gate of which is applied the address signal and the clock-including address signal, respectively, whereby a terminal connecting the MOS transistor of one conductivity-type and the MOS transistors of the opposite conductivity-type serves as an output.

Abstract: A synergistic insecticidal composition comprises as a first ingredient the .beta.-exotoxin of Bacillus thuringiensis or a metal salt thereof and has a second ingredient of one or more of the following chemical insecticides:O,o-diethyl-O-(2-isopropyl-4-methyl-6-pyrimidyl) thionophosphate,O,o-dimethyl, .alpha.,.alpha.,.alpha.-trichloro-1-hydroxyethyl phosphonate,.alpha.-methoxy-4H-1,3,2-benzodioxaphosphorin-2-thione,O,o,-dimethyl S-(.alpha.-(ethoxycarbonyl)benzyl) phosphorodithioate,O,o-dimethyl S-(4-chlorophenyl) phosphorothioateThe first and second ingredients are used generally in a ratio of about 0.5:1 to 2.0:1 and may be dispersed in a major portion of an agronomically acceptable carrier.