Abstract: To restrain decrease of display quality because of increases in flicker level and decrease of uniformity in screen luminance caused by increases in the overcharging effect when an amorphous metal oxide semiconductor or an organic semiconductor that has an field-effect mobility greater than amorphous silicon is used for pixel TFTs in a liquid crystal display device or organic EL display device. A new relational formula is derived for punch-through voltage in gray scale display, where the visibility of flicker, screen burn-in, and the like is high, and in-plane differential in counter electrode potential, which are an index of the overcharging effect. A design is made so as to satisfy conditions for decreasing the in-plane differential in counter electrode potential that have been newly derived on the basis of this formula to an allowable limit value or less.

Abstract: To restrain decrease of display quality because of increases in flicker level and decrease of uniformity in screen luminance caused by increases in the overcharging effect when an amorphous metal oxide semiconductor or an organic semiconductor that has an field-effect mobility greater than amorphous silicon is used for pixel TFTs in a liquid crystal display device or organic EL display device. A new relational formula is derived for punch-through voltage in gray scale display, where the visibility of flicker, screen burn-in, and the like is high, and in-plane differential in counter electrode potential, which are an index of the overcharging effect. A design is made so as to satisfy conditions for decreasing the in-plane differential in counter electrode potential that have been newly derived on the basis of this formula to an allowable limit value or less.

Abstract: In wafer probe inspection for a flip-chip semiconductor device having a solder bump, electric test may be performed at a high temperature by causing a probe needle to directly contact a solder bump over a wafer. The inventors have examined such high temperature probe tests in various ways and revealed the following problems. When a high temperature probe test is performed at 90° C. or higher using a palladium alloy probe needle, tin diffusion due to a solder bump occurs at the needle point to raise resistance, resulting in causing open failure. According to the invention of the present application, at least the tip of a palladium-based probe needle has mainly a granular grain structure in a high temperature probe test performed with the palladium-based probe needle contacting a solder bump electrode over a semiconductor wafer.

Abstract: In wafer probe inspection for a flip-chip semiconductor device having a solder bump, electric test may be performed at a high temperature by causing a probe needle to directly contact a solder bump over a wafer. The inventors have examined such high temperature probe tests in various ways and revealed the following problems. When a high temperature probe test is performed at 90° C. or higher using a palladium alloy probe needle, tin diffusion due to a solder bump occurs at the needle point to raise resistance, resulting in causing open failure. According to the invention of the present application, at least the tip of a palladium-based probe needle has mainly a granular grain structure in a high temperature probe test performed with the palladium-based probe needle contacting a solder bump electrode over a semiconductor wafer.

Abstract: A substrate for display device is provided. As a wiring structure of the substrate, the scan line layer and the signal line layer are not connected directly by arranging through-holes between the scan line layer and the signal line layer, but are connected through an ITO layer by arranging through-holes between the scan line layer and the ITO layer and arranging through-holes between the signal line layer and the ITO layer, with an object to reduce the value of the connection resistance between the scan line layer and the signal line layer. Through-holes connecting the scan line layer and the ITO layer and through-holes connecting the signal line layer and the ITO layer are configured in a comb shape respectively and engaged with each other. Thus the length of the ITO connecting the scan line layer and the signal line layer becomes shorter and the value of the connection resistance is reduced.

Abstract: A liquid crystal display (LCD) device has a wiring structure of superfine wiring, wherein it can reduce the occurrence rate of electrostatic discharge (ESD), and the time constant of the scan line can be improved simultaneously. The wiring width in the portions of the scan lines where they intersect the auxiliary capacitance bunching lines is narrowed, so that the area of the intersection and the wiring capacitance is reduced, thus the time constant of the scan line is decreased, meanwhile, the wiring width in portions of the auxiliary capacitance lines where they intersect the auxiliary capacitance bunching line is enlarged, the distance between the adjacent scan line and the nearest portion of the auxiliary capacitance line is shortened, and the ESD occurs at the nearest portion, and the failure products caused by the ESD can be decreased.

Abstract: The present invention relates to a thin film transistor array substrate with multiple chamfers and liquid crystal display device. A wiring structure is provided on the thin film transistor array substrate with multiple chamfers which is used for producing a plurality of thin film transistor arrays from a mother substrate, said wiring structure allows the chamfer quantity to be confirmed easily in the chamfer process for cutting off the corners of the terminal face after the cutting off process for taking out the respective thin film transistor arrays, meanwhile, the OLB pads is not easy to be peeled off from the substrate, and the probability that the OLB pads are peeled off can be reduced.

Abstract: The invention provides wiring, which can form or disconnect freely the adjacent exposure regions by employing the same optical mask under a condition that a plurality of array substrates are produced on one mother glass substrate; and an optical mask, which can be inspected by utilizing the same probe device for inspecting even though under a condition that the same mother glass substrate is used to produce the array substrates with different sizes; array substrates; and the manufacture method of the same.

Abstract: The present invention relates to a thin film transistor array substrate with multiple chamfers and liquid crystal display device. A wiring structure is provided on the thin film transistor array substrate with multiple chamfers which is used for producing a plurality of thin film transistor arrays from a mother substrate, said wiring structure allows the chamfer quantity to be confirmed easily in the chamfer process for cutting off the corners of the terminal face after the cutting off process for taking out the respective thin film transistor arrays, meanwhile, the OLB pads is not easy to be peeled off from the substrate, and the probability that the OLB pads are peeled off can be reduced.

Abstract: A substrate for display device is provided. As a wiring structure of the substrate, the scan line layer and the signal line layer are not connected directly by arranging through-holes between the scan line layer and the signal line layer, but are connected through an ITO layer by arranging through-holes between the scan line layer and the ITO layer and arranging through-holes between the signal line layer and the ITO layer, with an object to reduce the value of the connection resistance between the scan line layer and the signal line layer. Through-holes connecting the scan line layer and the ITO layer and through-holes connecting the signal line layer and the ITO layer are configured in a comb shape respectively and engaged with each other. Thus the length of the ITO connecting the scan line layer and the signal line layer becomes shorter and the value of the connection resistance is reduced.

Abstract: The object of the present invention is to provide a liquid crystal display device, which can be used in the active matrix type liquid crystal display device and has a wiring structure of superfine wiring, and a method for manufacturing the liquid crystal display device, wherein it can reduce the occurrence rate of the failures caused by the static electricity which damages the insulating layer of the electrodes or between the electrodes in the manufacturing process, and the time constant of the scan line can be improved simultaneously.

Abstract: In matrix array substrate for flat-panel display devices or the like in which a repair circuit for connecting a defected pixel electrode and next electrode in a tandem is disposed between the two pixel electrodes, a contact hole for connecting one of connector electrodes of the repair circuit to one of the pixel electrodes is disposed within contours of a scanning line. Meanwhile, in a matrix array substrate for normally white mode flat-panel display devices, an island metal pattern is disposed within the contours of a scanning line and within a storage-capacity-forming portion extended from one of the two electrodes. The island metal pattern is formed simultaneously with signal line and has a scanning-line-wise size larger than width of the scanning line.

Abstract: A control device of an IPS-mode or other mode liquid crystal display device for increasing response speed without diminishing elastic torque of the liquid crystal. Image signals are supplied in such a manner that one display pattern is displayed in first and second, two consecutive frames. When to increase voltage of the image signal for changing luminance, voltage at the first frame being set higher than a voltage value of gradation scale corresponding to a given luminance; and voltage at the second frame being set to a voltage value of gradation scale corresponding to the given luminance. Meanwhile, when to decrease voltage of the image signal for changing luminance, voltage at the first frame being set lower than a voltage value of gradation scale corresponding to a given luminance; and voltage at the second frame being set to a voltage value of gradation scale corresponding to the given luminance.

Abstract: A control device of an IPS-mode or other mode liquid crystal display device for increasing response speed without diminishing elastic torque of the liquid crystal. Image signals are supplied in such a manner that one display pattern is displayed in first and second, two consecutive frames. When to increase voltage of the image signal for changing luminance, voltage at the first frame being set higher than a voltage value of gradation scale corresponding to a given luminance; and voltage at the second frame being set to a voltage value of gradation scale corresponding to the given luminance. Meanwhile, when to decrease voltage of the image signal for changing luminance, voltage at the first frame being set lower than a voltage value of gradation scale corresponding to a given luminance; and voltage at the second frame being set to a voltage value of gradation scale corresponding to the given luminance.

Abstract: In matrix array substrate for flat-panel display devices or the like in which a repair circuit for connecting a defected pixel electrode and next electrode in a tandem is disposed between the two pixel electrodes, a contact hole for connecting one of connector electrodes of the repair circuit to one of the pixel electrodes is disposed within contours of a scanning line. Meanwhile, in a matrix array substrate for normally white mode flat-panel display devices, an island metal pattern is disposed within the contours of a scanning line and within a storage-capacity-forming portion extended from one of the two electrodes. The island metal pattern is formed simultaneously with signal line and has a scanning-line-wise size larger than width of the scanning line.

Abstract: A step portion is formed in an insulating layer provided between two opposing electrode layers outside a pixel electrode formation region, so that a projection portions are formed on the two electrode layers, wherein the shape of the projection portions of the electrode layers is of an electric-field concentration type to induce discharging between the opposing portions of the layers via the insulating layer.

Abstract: It is an object of the invention to provide an electrode wire for an electrical discharge machining apparatus, which is low-priced in cost of production, has sufficient conductivity and strength at high temperature and is suited for improving the speed of electrical discharge machining. Cu—Zn alloy covering layer is formed around a core metallic wire formed of Cu—0.02 to 0.2 Zr alloy or Cu—0.15 to 0.25 Sn—0.15 to 0.25 In alloy.

Abstract: A number of pixel regions surrounded by scanning signal lines and display signal lines are defined on an array substrate of a liquid crystal display element. Formed in each pixel region are a display pixel electrode extending in parallel with the display signal lines and two opposite electrodes provided on both sides of the display pixel electrode and extending in parallel with the display pixel electrode. Each of the two opposite electrodes is provided at a predetermined interval from the display pixel electrode. An end of the display pixel electrode is layered over an opposite signal line, thereby constituting a first supplemental capacity, and another end thereof is electrically connected to a switching element. An end of each opposite electrode is electrically connected to an opposite signal line. The display pixel electrode and the opposite electrodes are formed by processing the same conductive layer as that forming the display signal lines.

Abstract: It is an object of the invention to provide an electrode wire for an electrical discharge machining apparatus, which is low-priced in cost of production, has sufficient conductivity and strength at high temperature and is suited for improving the speed of electrical discharge machining. Cu—Zn alloy covering layer is formed around a core metallic wire formed of Cu-0.02 to 0.2 Zr alloy or Cu-0.15 to 0.25 Sn-0.15 to 0.25 In alloy.

Abstract: The invention relates to a method for manufacturing an electrode wire for an electrical discharge machining apparatus, which is composed of a core wire formed of Cu or Cu-alloy and a covering layer formed of brass. A brass tape is longitudinally applied around a core wire to provide a pipe, a seam formed by butting longitudinal edges of the brass tape is continuously welded to provide a composite wire, area-reduction process of reduction rate less than 65% is applied to the brass pipe by means of a squeezing die, a heat treatment at a temperature higher a recrystallization one of brass is applied to the composite pipe, and thereafter the composite wire is processed to be reduced in area through plural reducing dies step by step.