Patents by Inventor Hideo Kubota

Hideo Kubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7464210
    Abstract: This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same interrupt exception handling routine if the request event occurs a plurality of times. A software interrupt counter or a hardware interrupt counter for retaining the number of times of occurrence of an interrupt request generation event counts up when a software processing which generates a software interrupt or a hardware event that generates a hardware interrupt occurs, and counts down when a CPU performs a processing for removing the interrupt request. If the value of the software interrupt counter and the value of the hardware interrupt counter are not zero, a software interrupt request signal and a hardware interrupt request signal to the CPU are asserted.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: December 9, 2008
    Assignees: Renesas Technology Corp., Denso Corporation
    Inventors: Masafumi Inoue, Takanaga Yamazaki, Takeshi Kataoka, Hideo Kubota, Satoshi Tanaka, Hirokazu Komori, Takahiro Gotoh
  • Patent number: 7020764
    Abstract: A useful semiconductor processing device (LSI) is capable of implementing the precise setting of signals at the final stage of user system development and enabling the user to build a logic circuit in the device in a very short time. The LSI includes a CPU, a flash memory which is a nonvolatile memory, a programmable logic which is a SRAM-type field programmable gate array, and a configuration circuit which implements the logic circuit configuration operation. At the event of power-on reset, logic building data stored in the flash memory is transferred to the programmable logic to establish a logic circuit in it under control of the configuration circuit, so that the logic circuit built in the programmable logic can be used immediately after the power-on reset of the device.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: March 28, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hideo Kubota, Takanaga Yamazaki
  • Publication number: 20050193156
    Abstract: This invention provides a data processing system capable of performing an interrupt exception handling routine as many times as the number of times of occurrence of a request event for the same interrupt exception handling routine if the request event occurs a plurality of times. A software interrupt counter or a hardware interrupt counter for retaining the number of times of occurrence of an interrupt request generation event counts up when a software processing which generates a software interrupt or a hardware event that generates a hardware interrupt occurs, and counts down when a CPU performs a processing for removing the interrupt request. If the value of the software interrupt counter and the value of the hardware interrupt counter are not zero, a software interrupt request signal and a hardware interrupt request signal to the CPU are asserted.
    Type: Application
    Filed: January 19, 2005
    Publication date: September 1, 2005
    Inventors: Masafumi Inoue, Takanaga Yamazaki, Takeshi Kataoka, Hideo Kubota, Satoshi Tanaka, Hirokazu Komori, Takahiro Gotoh
  • Publication number: 20040017724
    Abstract: A useful semiconductor processing device (LSI) is capable of implementing the precise setting of signals at the final stage of user system development and enabling the user to build a logic circuit in the device in a very short time. The LSI includes a CPU, a flash memory which is a nonvolatile memory, a programmable logic which is a SRAM-type field programmable gate array, and a configuration circuit which implements the logic circuit configuration operation. At the event of power-on reset, logic building data stored in the flash memory is transferred to the programmable logic to establish a logic circuit in it under control of the configuration circuit, so that the logic circuit built in the programmable logic can be used immediately after the power-on reset of the device.
    Type: Application
    Filed: July 18, 2003
    Publication date: January 29, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Hideo Kubota, Takanaga Yamazaki
  • Patent number: 3969311
    Abstract: In accordance with a preferred embodiment of this invention, a fiber reinforced polyester article having a low surface profile is produced from a material which may be used either as a bulk molding or as a sheet molding compound. Preferably, this composition is produced from a formulation comprising about equal proportions of (1) an unsaturated polyester condensation product dissolved in (2) a copolymerizable reactive diluent solution of from proportionally 11/2 to 2 parts by weight of tertiary butyl styrene per each part of styrene. This formulation will of course also contain a filler such as a particulate calcium carbonate and reinforcing glass fibers. It is the specific combination of styrene and tertiary butyl styrene which promotes the low profile surface in the final molded article.
    Type: Grant
    Filed: April 3, 1975
    Date of Patent: July 13, 1976
    Assignee: General Motors Corporation
    Inventor: Hideo Kubota