Abstract: A conductive C-plane GaN substrate has a resistivity of 2×10?2 ?·cm or less or an n-type carrier concentration of 1×1018 cm?3 or more at room temperature. At least one virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate. The line segment satisfies at least one of the following conditions (A1) and (B1): (A1) when an XRC of (004) reflection is measured at 1 mm intervals on the line segment, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec; and (B1) when an XRC of the (004) reflection is measured at 1 mm intervals on the line segment, a difference between maximum and minimum values of XRC peak angles across all the measurement points is less than 0.2°.

Abstract: To provide a polypeptide having heparosan-glucuronate 5-epimerase activity, whereby means for producing a polysaccharide in which hexuronic acid residues has been epimerized is provided. Through screening of Achatina fulica cDNA library, a DNA encoding a polypeptide of heparosan-glucuronate 5-epimerase is obtained. The epimerase acts on glucuronic acid residues of N-acetyl heparosan and/or iduronic acid residues of completely desulfated N-acetylated heparin. The polypeptide encoded by the DNA is expressed by insect cells, to thereby yield the polypeptide having heparosan-glucuronate 5-epimerase activity. By bringing the polypeptide into contact with N-acetyl heparosan or completely desulfated N-acetylated heparin, a polysaccharide in which hexuronic acid residues has been epimerized is yielded.

Abstract: To provide a polypeptide having heparosan-glucuronate 5-epimerase activity, whereby means for producing a polysaccharide in which hexuronic acid residues has been epimerized is provided. Through screening of Achatina fulica cDNA library, a DNA encoding a polypeptide of heparosan-glucuronate 5-epimerase is obtained. The epimerase acts on glucuronic acid residues of N-acetyl heparosan and/or iduronic acid residues of completely desulfated N-acetylated heparin. The polypeptide encoded by the DNA is expressed by insect cells, to thereby yield the polypeptide having heparosan-glucuronate 5-epimerase activity. By bringing the polypeptide into contact with N-acetyl heparosan or completely desulfated N-acetylated heparin, a polysaccharide in which hexuronic acid residues has been epimerized is yielded.

Abstract: There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access. An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.

Abstract: A glycosaminoglycan sulfotransferase, a peptide thereof, a nucleic acid comprising a nucleotide sequence encoding the same, an enzyme agent for the synthesis of a glycosaminoglycan, which comprises the above-described enzyme or polypeptide, and a process for producing a glycosaminoglycan, which uses the enzyme agent.

Abstract: There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access. An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.

Abstract: A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a delay amount of the received data based on the delay set value. The delay set value is stored in both the delay holding section of the memory controller and the DRAM.

Abstract: There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access. An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.

Abstract: There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access. An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.

Abstract: A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a delay amount of the received data based on the delay set value. The delay set value is stored in both the delay holding section of the memory controller and the DRAM.

Abstract: A memory controller transmits and receives data to and from a memory. The memory controller includes a delay control section deciding a set value indicative of a determined delay amount in response to a result of a comparison between a test data transmitted to the memory and test data received from the memory, and transmitting the decided set value to the memory, a taking-in section receiving the set value stored in the memory, and a delay adjustment section receiving data from the memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section.

Abstract: There is a need to provide a small-sized memory interface circuit capable of adjusting timing between a strobe signal and a data signal without interrupting a normal memory access. An expected value acquisition latch latches write data in synchronization with a clock signal. A WDLL outputs a write strobe signal WDQS. An RDLL outputs a delayed write strobe signal WDQS_d. A read data latch latches looped-back write data in synchronization with the delayed write strobe signal WDQS_d. A comparator compares the read data latch with an output from the expected value acquisition latch. A register portion stores a delay value to be placed in the RDLL. A register control portion updates a delay value in the register portion in accordance with a comparison result. A delay selection portion places a delay value read from the register portion in the RDLL.

Abstract: A self-diagnostic circuit includes a setting unit receiving a plurality of detection signals generated in an integrated circuit device, and determining a type of detection signal to be detected among the received plurality of detection signals. A counter is coupled to the setting unit and counts a number of a signal corresponding to the type of the detection signal to be detected.

Abstract: A memory controller transmits and receives data to and from a memory. The memory controller includes a delay control section deciding a set value indicative of a determined delay amount in response to a result of a comparison between a test data transmitted to the memory and test data received from the memory, and transmitting the decided set value to the memory, a taking-in section receiving the set value stored in the memory, and a delay adjustment section receiving data from the memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section.

Abstract: A self-diagnostic circuit includes a setting unit receiving a plurality of detection signals generated in an integrated circuit device, and determining a type of detection signal to be detected among the received plurality of detection signals. A counter is coupled to the setting unit and counts a number of a signal corresponding to the type of the detection signal to be detected.

Abstract: A glycosaminoglycan sulfotransferase, a peptide thereof, a nucleic acid comprising a nucleotide sequence encoding the same, an enzyme agent for the synthesis of a glycosaminoglycan, which comprises the above-described enzyme or polypeptide, and a process for producing a glycosaminoglycan, which uses the enzyme agent.

Abstract: In a semiconductor device, a main circuit is operated by a first clock signal, and at least one characteristic evaluating circuit is operated by a second clock signal whose frequency is higher than a frequency of the first clock signal. Also, at least one deterioration detecting circuit is connected to the characteristic evaluating circuit and Is adapted to detect deterioration of the characteristic evaluating circuit.

Abstract: A glycosaminoglycan sulfotransferase, a peptide thereof, a nucleic acid comprising a nucleotide sequence encoding the same, an enzyme agent for the synthesis of a glycosaminoglycan, which comprises the above-described enzyme or polypeptide, and a process for producing a glycosaminoglycan, which uses the enzyme agent.

Abstract: In a semiconductor device, a main circuit is operated by a first clock signal, and at least one characteristic evaluating circuit is operated by a second clock signal whose frequency is higher than a frequency of the first clock signal. Also, at least one deterioration detecting circuit is connected to the characteristic evaluating circuit and Is adapted to detect deterioration of the characteristic evaluating circuit.

Abstract: A glycosaminoglycan sulfotransferase, a peptide thereof, a nucleic acid comprising a nucleotide sequence encoding the same, an enzyme agent for the synthesis of a glycosaminoglycan, which comprises the above-described enzyme or polypeptide, and a process for producing a glycosaminoglycan, which uses the enzyme agent.