Abstract: A data reception device that can improve communication quality when transmitting/receiving serial data is to be provided. There is provided the data reception device including a signal generation unit that generates, from serial data received, a first signal whose value is inverted at a rising timing of the serial data and a second signal whose value is inverted at a falling timing of the serial data, and a clock recovery unit that performs clock recovery using the first signal and the second signal generated by the signal generation unit.

Abstract: A data reception device that can improve communication quality when transmitting/receiving serial data is to be provided. There is provided the data reception device including: a signal generation unit that generates, from serial data received, a first signal whose value is inverted at a rising timing of the serial data and a second signal whose value is inverted at a falling timing of the serial data; and a clock recovery unit that performs clock recovery using the first signal and the second signal generated by the signal generation unit.

Abstract: Disclosed herein is a data reproduction circuit including: a comparator configured to compare input data resulting from capacitive coupling with a comparison voltage as a threshold voltage and output a comparison result; and a comparison voltage variable section configured to change the comparison voltage along a mark rate of the input data and supply the changed comparison voltage to the comparator.

Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: A phase adjustment circuit includes: a serial-to-parallel conversion section configured to convert serial data including a synchronization pattern inserted into a predetermined position into parallel data in response to a clock; a synchronization-pattern-position detection section configured to detect the position of the synchronization pattern in the parallel data generated by the serial-to-parallel conversion section; and an adjustment section configured to adjust the phases of the parallel data and the clock to conform to a position detected by the synchronization-pattern-position detection section as the position of the synchronization pattern in accordance with information on the position of the synchronization pattern.

Abstract: A signal processing circuit having a modulator having frequency conversion circuits, each having a local oscillator and a mixer. The circuit multiplies a signal having a first frequency and a local oscillation signal from the local oscillator at the mixer to convert the frequency of the first frequency signal to a second frequency, outputs a current format frequency converted signal and a first gain control circuit amplifying the current format frequency converted signals from the frequency conversion circuits by a first gain in accordance with a first control voltage. The circuit also outputs the current format amplified signals and a second gain control circuit connected after the first gain control circuit and having at least one gain control circuit which amplifies a current format amplified signal output from the first gain control circuit by a second gain.

Abstract: Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

Abstract: An automatic gain control circuit able to perform high speed and correct level acquisition, able to prevent occurrence of error, and able to prevent a crash of the system. An amplification gain controller outputs a gain control signal to an automatic gain control amplifier to amplify the received signal with maximum value when receiving a burst detection trigger signal. A second gain control signal based on the detected reception signal power is calculated when receiving a first burst synchronization detection signal; and this second gain control signal is output to the automatic gain control amplifier. A received digital signal is amplified with the second gain and integrated to find the reception signal power, from which a third gain control signal is calculated and outputted to the automatic gain control amplifier to amplify the received signal with this third gain.

Abstract: A signal processing circuit having a modulator (10B) having frequency conversion circuits (15, 16) each having a local oscillator and mixer, multiplying a signal having a first frequency and a local oscillation signal from the local oscillator at the mixer to convert the frequency of the first frequency signal to a second frequency, and outputting a current format frequency converted signal and a first gain control circuit (18) amplifying the current format frequency converted signals from the frequency conversion circuits (15, 16) by a first gain in accordance with a first control voltage (Vc) and outputting the current format amplified signals and a second gain control circuit (10C) connected after the first gain control circuit (18) and having at least one gain control circuit (19, 20) amplifying a current format amplified signal output from the first gain control circuit (18) by a second gain in accordance with a second control voltage (Vc) and outputting an amplified signal.

Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.

Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.

Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.

Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.

Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.

Abstract: An automatic gain control circuit able to perform high speed and correct level acquisition, able to prevent occurrence of error, and able to prevent a crash of the system, a method of same, and a demodulation apparatus, provided with an amplification gain controller 211 for outputting a gain control signal to an automatic gain control amplifier 201 so as to amplify the reception signal with the maximum value when receiving a burst detection starting use trigger signal, calculating a second gain based on a reception signal power value detected at a reception signal power monitor 202 when receiving a first burst synchronization detection signal from the burst detector, outputting the gain control signal to the automatic gain control amplifier 201 so as to amplify the reception signal with the second gain, receiving the digital reception signal amplified with the second gain and integrating the same to find the reception signal power value, calculating a third gain based on the found reception signal power value

Abstract: A grounded emitter amplifier and a radio communication device using the same in which a bias voltage is generated in order to adjust an emitter current of a transistor in a grounded emitter amplification circuit so that the emitter current does not receive an influence of variations in several parameters of the transistor such as a current amplification factor hfe.

Abstract: A grounded emitter amplifier and a radio communication device using the same in which a bias voltage is generated in order to adjust an emitter current of a transistor in a grounded emitter amplification circuit so that the emitter current does not receive an influence of variations in several parameters of the transistor such as a current amplification factor hfe.

Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage as to compensate a linearity of the variable gain circuit to an extent of the external control voltage where the variable gain circuit loses a linearity. This gain control circuit is applied to an AGC circuit of a transmitting stage in a CDMA type mobile phone.