Patents by Inventor Hideo Mutou

Hideo Mutou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    Publication number: 20180277456
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 27, 2018
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Semiconductor device manufacturing method and semiconductor device
    Patent number: 10002808
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 19, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    Publication number: 20170092554
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: December 14, 2016
    Publication date: March 30, 2017
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    Publication number: 20150235973
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Semiconductor chip with modified regions for dividing the chip
    Patent number: 9070560
    Abstract: A semiconductor wafer with modified regions formed in the substrate is provided. A modified region is formed apart from the side of a wafer and a pad is formed over an insulating film, which is formed over the main surface of the substrate of the wafer. Further, the modified region is formed closer to the side surface of the substrate than the pad. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: June 30, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    Publication number: 20140252643
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Semiconductor device manufacturing method using laser irradiation and dicing saw and semiconductor device thereof
    Patent number: 8772135
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: July 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    Publication number: 20120077332
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: December 2, 2011
    Publication date: March 29, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Semiconductor device manufacturing method comprising a metal pattern and laser modified regions in a cutting region
    Patent number: 8084334
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • SEMICONDUCTOR DEVICE MANUFACTURING METHOD COMPRISING A METAL PATTERN AND LASER MODIFIED REGIONS IN A CUTTING REGION
    Publication number: 20110124180
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Semiconductor device manufacturing method comprising a metal pattern and laser modified regions in a cutting region
    Patent number: 7892949
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: February 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR
    Publication number: 20090121337
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 14, 2009
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino