Patents by Inventor Hideo Nakayoshi

Hideo Nakayoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7071576
    Abstract: A semiconductor device includes a semiconductor substrate, a first wiring arranged on the semiconductor substrate, a first electrode pad electrically connected to the first wiring, and a porous organic resin film covering the front surface of the semiconductor substrate such that the first electrode pad is exposed to the outside.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: July 4, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Nakayoshi, Chiaki Takubo
  • Publication number: 20050006766
    Abstract: A semiconductor device includes a semiconductor substrate, a first wiring arranged on the semiconductor substrate, a first electrode pad electrically connected to the first wiring, and a porous organic resin film covering the front surface of the semiconductor substrate such that the first electrode pad is exposed to the outside.
    Type: Application
    Filed: May 17, 2004
    Publication date: January 13, 2005
    Inventors: Hideo Nakayoshi, Chiaki Takubo
  • Patent number: 6337258
    Abstract: Grooves are formed in an element formation surface of a wafer along dicing lines or chip dividing lines. The grooves are deeper than a thickness of a finished chip. A holding member is attached on the element formation surface of the wafer. A bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. The chips are transferred while being held by porous adsorption.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: January 8, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Nakayoshi, Shinya Takyu, Keisuke Tokubuchi, Tetsuya Kurosawa
  • Patent number: 6294439
    Abstract: Grooves are formed in a surface of a wafer, on which semiconductor elements are formed, along dicing lines or chip parting lines on the wafer. The grooves are deeper than the thickness of a finished chip, and each of them has a curved bottom surface. A holding sheet is attached on the surface of the wafer on which the semiconductor elements are formed. Subsequently, the rear surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. Even after the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip. The lapping and polishing amount required to attain the thickness of the finished chip after the lapped face of the wafer reaches the bottom surface of the groove, and a depth of a region of the curved bottom surface of the groove define a ratio of not less than 0.3.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: September 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Sasaki, Shinya Takyu, Keisuke Tokubuchi, Koichi Yazima, Hideo Nakayoshi
  • Patent number: 6184109
    Abstract: Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines on the wafer by means of a dicing blade. The grooves are deeper than a thickness of a finished chip. Alternatively, grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along chip parting lines on the wafer by etching. Like the grooves described above, the grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. The bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.
    Type: Grant
    Filed: January 21, 1999
    Date of Patent: February 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Sasaki, Shinya Takyu, Keisuke Tokubuchi, Koichi Yazima, Hideo Nakayoshi
  • Patent number: 5107325
    Abstract: A semiconductor device comprises a semiconductor chip with an active surface having output bonding pads to which a plurality of conductive leads or finger contacts are attached via a TAB method and is packaged onto an insulating substrate having a pattern of conductors on its surface. The active surface of the semiconductor chip is initially coated with a first resin sealant comprising moldable resin agent containing a volatile solvent in the range of about 30% to 80% by volume, the solvent being soluble in the resin agent and having a volatility at a temperature below the thermosetting temperature of the resin agent. The semiconductor device is then mounted on the insulating substrate with the chip leads in aligned relation with at least some of the pattern conductors resulting in a cavity between the active circuit surface coated with the first resin sealant and the substrate surface.
    Type: Grant
    Filed: April 11, 1990
    Date of Patent: April 21, 1992
    Assignee: Seiko Epson Corporation
    Inventor: Hideo Nakayoshi