Patents by Inventor Hideo Numata
Hideo Numata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11799104Abstract: A fuel cell system includes a fuel cell stack, a fuel gas supply channel, a fuel gas circulation channel, a circulating pump that is driven by a pump motor having no rotation detecting sensor, and an ECU. When a method for operating the fuel cell system determines that the circulating pump is frozen in a low-temperature environment, the method performs a first step of performing a brake mode to limit the rotation of the pump motor while passing current to the pump motor, to thereby heat the pump motor. The method further performs a second step of, after rotating the pump motor, determining that the circulating pump has unfrozen if the rotational speed of the pump motor exceeds a given value.Type: GrantFiled: March 26, 2021Date of Patent: October 24, 2023Assignee: Honda Motor Co., Ltd.Inventors: Nobuki Koiwa, Masaoki Inamoto, Hideo Numata
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Patent number: 11705445Abstract: In a semiconductor device manufacturing method, a stacked substrate is formed. In the stacked substrate, a substrate is stacked repeatedly multiple times. The substrate includes a plurality of chip regions. In the semiconductor device manufacturing method, the stacked substrate is cut in a stacking direction among the plurality of chip regions, to separate the stacked substrate into a plurality of stacked bodies. In forming the stacked substrate, a first main surface of a first substrate and a second main surface of a second substrate are bonded to each other. In forming the stacked substrate, in a state where the second main surface is bonded to the first main surface, a third main surface of the second substrate opposite to the second main surface is thinned. In forming the stacked substrate, the third main surface of the second substrate and a fourth main surface of a third substrate are bonded to each other.Type: GrantFiled: August 27, 2021Date of Patent: July 18, 2023Assignee: KIOXIA CORPORATIONInventor: Hideo Numata
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Publication number: 20220293581Abstract: In a semiconductor device manufacturing method, a stacked substrate is formed. In the stacked substrate, a substrate is stacked repeatedly multiple times. The substrate includes a plurality of chip regions. In the semiconductor device manufacturing method, the stacked substrate is cut in a stacking direction among the plurality of chip regions, to separate the stacked substrate into a plurality of stacked bodies. In forming the stacked substrate, a first main surface of a first substrate and a second main surface of a second substrate are bonded to each other. In forming the stacked substrate, in a state where the second main surface is bonded to the first main surface, a third main surface of the second substrate opposite to the second main surface is thinned. In forming the stacked substrate, the third main surface of the second substrate and a fourth main surface of a third substrate are bonded to each other.Type: ApplicationFiled: August 27, 2021Publication date: September 15, 2022Applicant: Kioxia CorporationInventor: Hideo NUMATA
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Patent number: 11444294Abstract: A fuel cell system includes a fuel cell stack, a fuel gas supply channel, a fuel gas circulation channel, a circulating pump that is driven by a pump motor having no sensor, and an ECU for controlling the rotation of the pump motor. A method for operating the fuel cell system rotates the pump motor when starting, and stops the supply of electric power to the pump motor after the rotational speed of the pump motor has reached a given value, and determines, in an inertial period, whether or not the rotational speed of the pump motor has become equal to or lower than a predetermined value within a given time period.Type: GrantFiled: March 26, 2021Date of Patent: September 13, 2022Assignee: Honda Motor Co., Ltd.Inventors: Yusai Yoshimura, Hideo Numata, Nobuki Koiwa
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Patent number: 11398635Abstract: A fuel cell system includes a fuel cell stack, a fuel gas supply channel, a circulation passage, a purge valve, and a temperature sensor. A method of operating the fuel cell system performs a judging step of determining whether or not the temperature detected by the temperature sensor is at or below a given temperature. Then, if the temperature is at or below the given temperature, the method performs a purge valve scavenging process step of intermittently opening and closing the purge valve multiple times, while supplying the fuel gas through the fuel gas supply channel.Type: GrantFiled: March 30, 2021Date of Patent: July 26, 2022Assignee: Honda Motor Co., Ltd.Inventors: Nobuki Koiwa, Hideo Numata, Jumpei Ogawa, Yusai Yoshimura
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Publication number: 20210305599Abstract: A fuel cell system includes a fuel cell stack, a fuel gas supply channel, a circulation passage, a purge valve, and a temperature sensor. A method of operating the fuel cell system performs a judging step of determining whether or not the temperature detected by the temperature sensor is at or below a given temperature. Then, if the temperature is at or below the given temperature, the method performs a purge valve scavenging process step of intermittently opening and closing the purge valve multiple times, while supplying the fuel gas through the fuel gas supply channel.Type: ApplicationFiled: March 30, 2021Publication date: September 30, 2021Inventors: Nobuki KOIWA, Hideo NUMATA, Jumpei OGAWA, Yusai YOSHIMURA
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Publication number: 20210305600Abstract: A fuel cell system includes a fuel cell stack, a fuel gas supply channel, a fuel gas circulation channel, a circulating pump that is driven by a pump motor having no rotation detecting sensor, and an ECU. When a method for operating the fuel cell system determines that the circulating pump is frozen in a low-temperature environment, the method performs a first step of performing a brake mode to limit the rotation of the pump motor while passing current to the pump motor, to thereby heat the pump motor. The method further performs a second step of, after rotating the pump motor, determining that the circulating pump has unfrozen if the rotational speed of the pump motor exceeds a given value.Type: ApplicationFiled: March 26, 2021Publication date: September 30, 2021Inventors: Nobuki KOIWA, Masaoki INAMOTO, Hideo NUMATA
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Publication number: 20210305596Abstract: A fuel cell system includes a fuel cell stack, a fuel gas supply channel, a fuel gas circulation channel, a circulating pump that is driven by a pump motor having no sensor, and an ECU for controlling the rotation of the pump motor. A method for operating the fuel cell system rotates the pump motor when starting, and stops the supply of electric power to the pump motor after the rotational speed of the pump motor has reached a given value, and determines, in an inertial period, whether or not the rotational speed of the pump motor has become equal to or lower than a predetermined value within a given time period.Type: ApplicationFiled: March 26, 2021Publication date: September 30, 2021Inventors: Yusai YOSHIMURA, Hideo NUMATA, Nobuki KOIWA
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Patent number: 10862142Abstract: A flow rate adjustment structure includes: a fixed member including a fixed surface on which a fixed opening is formed; a movable member including a movable surface on which a movable opening is formed, and to be displaced relative to the fixed member; and an adjustment unit that variably adjusts an overlap area or an overlap frequency between the fixed opening and the movable opening by relatively displacing the movable surface along the fixed surface.Type: GrantFiled: November 26, 2018Date of Patent: December 8, 2020Assignee: Honda Motor Co., Ltd.Inventors: Yuji Okamura, Hideo Numata, Makoto Hattori
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Publication number: 20190165390Abstract: A flow rate adjustment structure includes: a fixed member including a fixed surface on which a fixed opening is formed; a movable member including a movable surface on which a movable opening is formed, and to be displaced relative to the fixed member; and an adjustment unit that variably adjusts an overlap area or an overlap frequency between the fixed opening and the movable opening by relatively displacing the movable surface along the fixed surface.Type: ApplicationFiled: November 26, 2018Publication date: May 30, 2019Inventors: Yuji OKAMURA, Hideo NUMATA, Makoto HATTORI
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Patent number: 9893116Abstract: A manufacturing method of an electronic device processes a surface of a first wafer, bonds a surface of a second wafer to the processed surface of the first wafer, thins the first wafer by polishing a back surface of the first wafer, the back surface being located on an opposite side of the processed surface, forms a groove along a periphery of the back surface of the thinned first wafer by using a dicing blade, attaches a protective layer to the back surface of the first wafer having the groove, via a bonding layer, and polishes a back surface of the second wafer, the back surface being located on an opposite side of the surface attached to the protective layer.Type: GrantFiled: March 13, 2015Date of Patent: February 13, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinya Takyu, Hideo Numata, Hiroyuki Okura
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Publication number: 20160079303Abstract: A manufacturing method of an electronic device processes a surface of a first wafer, bonds a surface of a second wafer to the processed surface of the first wafer, thins the first wafer by polishing a back surface of the first wafer, the back surface being located on an opposite side of the processed surface, forms a groove along a periphery of the back surface of the thinned first wafer by using a dicing blade, attaches a protective layer to the back surface of the first wafer having the groove, via a bonding layer, and polishes a back surface of the second wafer, the back surface being located on an opposite side of the surface attached to the protective layer.Type: ApplicationFiled: March 13, 2015Publication date: March 17, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinya Takyu, Hideo Numata, Hiroyuki Okura
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Publication number: 20150263212Abstract: According to one embodiment, a substrate for semiconductor devices includes a P-type semiconductor substrate, a P-type or N-type semiconductor layer, and a P-type or N-type epitaxial layer. The P-type or N-type semiconductor layer is provided at a surface layer of the semiconductor substrate and has a resistance value lower than a resistance value of the semiconductor substrate. The P-type or N-type epitaxial layer is provided on a surface of the semiconductor layer and has a resistance value higher than the resistance value of the semiconductor layer.Type: ApplicationFiled: March 2, 2015Publication date: September 17, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shinji UYA, Nagataka Tanaka, Mokuji Kageyama, Hideo Numata
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Publication number: 20150214193Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.Type: ApplicationFiled: April 2, 2015Publication date: July 30, 2015Inventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
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Patent number: 9024424Abstract: A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.Type: GrantFiled: August 16, 2012Date of Patent: May 5, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yoshimura, Naoyuki Komuta, Hideo Numata
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Patent number: 8980671Abstract: A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate.Type: GrantFiled: February 8, 2012Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Hongo, Kazumasa Tanida, Akihiro Hori, Kenji Takahashi, Hideo Numata
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Patent number: 8822307Abstract: According to one embodiment, a semiconductor manufacturing apparatus is provided. The semiconductor manufacturing apparatus includes a stage, a substrate supporter, first and second pushers, and a controller. The stage is configured to support outer periphery portions of the first semiconductor substrate from below. The substrate supporter is configured to hold the back of the second semiconductor substrate. The first and second pushers are configured to bring the first and second semiconductor substrates in contact. The controller is configured to form the bonding initiation point between the first and second semiconductor substrates.Type: GrantFiled: March 16, 2012Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Naoko Yamaguchi, Kazumasa Tanida, Hideo Numata, Satoshi Hongo, Kenji Takahashi
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Patent number: 8778778Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.Type: GrantFiled: August 18, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
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Patent number: 8748316Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes polishing a peripheral portion of the semiconductor substrate, and forming a protective film to be an insulating film, on a surface of the semiconductor substrate including a surface exposed by the polishing.Type: GrantFiled: June 27, 2011Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shirono, Mie Matsuo, Hideo Numata, Kazumasa Tanida, Tsuyoshi Matsumura
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Patent number: 8704337Abstract: In one embodiment, a method for manufacturing a semiconductor device includes following steps. An aperture is formed in an interlayer insulating film formed on a semiconductor wafer apart from an integrated circuit portion by etching process. The interlayer insulating film has a dielectric constant smaller than a silicon oxide film (SiO2), and the width of the aperture is larger than a dicing region. A resin layer is embedded in the aperture. An adhesive layer is formed on the interlayer insulating film and the resin layer. The semiconductor wafer is attached to a glass substrate using the adhesive layer by Face Down method. The semiconductor wafer, the resin layer, and the adhesive layer on a dicing region are cut by blade dicing. The semiconductor wafer and the glass substrate adhered to the semiconductor wafer are cut into pieces by the blade dicing of the glass substrate under the dicing region.Type: GrantFiled: September 13, 2010Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Takano, Hideo Numata, Kazumasa Tanida