Abstract: A toner composition that permits printing of clear-cut and high image quality without developing a fog or a blur is provided.

Abstract: A toner composition having a high light transmission when printed on a transparent medium, in addition to being superior in strength and durability is provided. Binder resin particles manufactured through a dispersing polymerization method are colored using at least one kind of dye and are then subjected to a process of injecting an organic finely divided powder and a charge controlling agent and to a process of externally adding a hydrophobic silica and a conductive titanium oxide, thereby making a toner composition having a gel percentage of 2 to 15%.

Abstract: The present invention provides a digital video receiving apparatus for displaying a plurality of digital TV pictures on a plurality of receiving terminal apparatuses. The digital video receiving apparatus includes a tuner for extracting the received digital TV multiplexed signal, a demodulator for decoding the digital signals provided from the tuner, a demultiplexer for demultiplexing the multiplexed signals outputted from the demodulator to obtain a bit stream including a video signal, an audio signal and a data signal. The digital video receiving apparatus further includes a video decoder, an audio decoder and a data decoder for decoding signals outputted from the demultiplexer. The digital video receiving apparatus decodes the input multiplexed digital TV signal and outputs a video signal, an audio signal and a data signal corresponding to respective programs.

Abstract: The present invention provides a digital video receiving apparatus for displaying a plurality of digital TV pictures on a plurality of receiving terminal apparatuses. The digital video receiving apparatus includes a tuner for extracting the received digital TV multiplexed signal, a demodulator for decoding the digital signals provided from the tuner, a demultiplexer for demultiplexing the multiplexed signals outputted from the demodulator to obtain a bit stream including a video signal, an audio signal and a data signal. The digital video receiving apparatus further includes a video decoder, an audio decoder and a data decoder for decoding signals outputted from the demultiplexer. The digital video receiving apparatus decodes the input multiplexed digital TV signal and outputs a video signal, an audio signal and a data signal corresponding to respective programs.

Abstract: Two-dimensional addresses of lateral lines of a rectangular area are produced in a prescribed scanning order in a sender-memory control unit as readout addresses of a sender's memory, pieces of pixel data corresponding to the readout addresses are read out from the sender's memory, the pieces of pixel data read out are sub-sampled at a sample ratio of n:1 in a direction of each lateral line according to a quincunx method in a data transforming unit, two-dimensional write addresses of a receiver's memory are produced in a receiver-memory control unit, and pieces of sub-sampled pixel data are written in the receiver's memory. Accordingly, the pieces of pixel data can be sub-sampled and transferred at a high speed in a DMA transfer apparatus.

Abstract: A data demultiplexer in a media demultiplexer dissolves a bit stream into video packets and audio packets. A CRC calculating unit subjects data from a CRC character isolating unit to the same calculation as performed at the encoding end and outputs a result of calculation to an error information adding unit. The error information adding unit compares the result of calculation with a CRC character attached to the video packet so as to determine whether they match. The error information adding unit adds error information based on a result of determination to the video packet. The resultant revised video packet is output to a video decoder via a buffer.

Abstract: A method and apparatus of digital image decoding is provided for reducing compression-related deterioration of an image to a minimum with a reduced storage capacity. The digital image decoding apparatus is equipped with a compression rate judging section for judging an optimal rate of compression for effecting the least deterioration to the image based upon the size of image in connection with the storage capacity of a frame memory. A compressing section compresses decoded data based upon the optimal rate of compression and sends the compressed data to a predictive/display frame memory for storage. An expanding A section expands the compressed data based upon the optimal rate of compression and sends the expanded data to a decoding section when the expanded data is required.

Abstract: A toner comprises toner particles which have been colored with a dye and have a volume mean diameter of several .mu.m, and to which silicone fine particles are externally added. A dry-development toner comprises resin particles having been colored with a dye, wherein the surfaces of resin particles are coated with a fine organic powder having a mean particle diameter of 0.8 .mu.m or less by means of mechanical impact force.

Abstract: In a multimedia information processing system, a relay station comprises: transmission decoding section for reproducing a fixed packets stream from received transmission signal from a transmitter; signal change processing means for executing changing process for the fixed packets stream; and transmission coding section for producing a transmission signal corresponding to a characteristic of a transmission line from the fixed packets stream. The construction for exchanging signals between different transmission means is simplified. Thus, it is achieved to exchange contents of media between different transmission means by a simple construction.

Abstract: A multimedia information processing apparatus comprises information source processing portions, element packet processing portions, packet processing portions, transmission path processing portions, an information source processing portion bus, an element packets processing bus and a packet multiplexing bus. A multimedia information processing apparatus is divided into a plurality of layers, and interface signals are defined between each processing portion and each processing is connected via buses. Contents such as broadcasting, communication and storage are secured by an editing unit comprised of a computer and by expansion of units via bus. Bus connection enables editing processing portions such as a complex processing portion including a plurality of processing portions and a computer to expand functions of a multimedia information processing apparatus.

Abstract: Data which has been decoded by a decoding portion 101 are compressed by a compressing portion 102 and stored in a prediction/display frame memory portion 103. From the data stored in the prediction/display frame memory portion 103, any data required for decoding other frames in the decoding portion 101 are decompressed through a decompressing A portion 104 and supplied to the decoding portion 101. Alternatively, data to be displayed is read from the prediction/display frame memory portion 103, decompressed at a decompressing B portion 105 and supplied to a display apparatus. Writing to and reading from the above-mentioned prediction/display frame memory portion 103 is controlled by an address controlling portion 106. Since compressed data are stored in the prediction/display frame memory portion 103, the memory capacity can be decreased.

Abstract: Data decoded by a decoding section (101) are compressed by a compressing section (102) and then stored in a forecast/display frame memory section (103). The data in the forecast/display frame memory section (103) which are required to decode the other frames in the decoding section (101) are expanded and supplied to the decoding section through an expanding A section (104). The decoding section (101) uses the data restored by the expanding operation to decode the image data subjected to the forecast encoding operation. On the other hand, the display frame is subjected to the expanding operation at an expanding B section (105) after it has been read out from the forecast/display frame memory section (103), the expanded display frame then being output and supplied to a display device. Thus, the data stored in the forecast/display frame memory section (103) can be compressed to reduce the size of memory capacity.

Abstract: A multimedia information processing system comprises an information-source coding section for generating an element packet containing coded multimedia information and additional information to specify the packet, a packet multiplexing section for generating multiplexed stream by multiplexing the element packet, and a transmission processing section for outputting the multiplexed stream as a transmission signal corresponding transmission media. In this multimedia information processing system, a processing sequence from selection of multimedia information to transmission or storage processing is classified, and the processing contents and input/output data are determined for each hierarchy. Data exchange between services such as broadcasting, communication, storage in computer and so on can be easily attained. Additionally, hardware structure of this system can be simplified, and additional functions can be easily added.

Abstract: A video codec (coder-decoder) system inputs consecutively admitted frames of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by internal coding circuits. This averages the numbers of significant pixels in the sub-sampled video data to be processed. The coded video data is composed so as to comply with specifications of the receiving equipment. Upon transmission, the data is again sub-sampled depending on the number of coding circuits on the receiving side. Each block of the sub-sampled data is given a header for consecutive transmission. This allows for a certain period of time between pieces of data that arrive at the receiving side, thereby eliminating time differences in receiving and coding.

Abstract: A digital signal processor having a DMA controller adapted for image processing while transmitting data between an internal memory and an external memory. The DMA controller includes a frame horizontal size register for representing a horizontal size of a two dimensional address space and block horizontal size register for representing a horizontal size of a rectangular portion in the two dimensional address space with a block address register for indicating a head address of source area, an internal memory start address register for representing a head address of destination area, and a word register. An address calculation unit in the DMA controller generates addresses based on two horizontal size register. An external data memory connecting unit in DSP for connecting the internal memory and the external memory has two modes. One is a mode of outputting an address in two machine cycles, and the other is a mode of outputting an address in one machine cycle.

Abstract: A maleic anhydride copolymer comprising maleic anhydride units (I), conjugated diene units (II) and aliphatic monoolefin units (III) is provided. This copolymer has a weight-average molecular weight of from 500 to 50000. The molar ratio of unit (I)/(unit (II)+unit (III)) ranges from 30/70 to 90/10 and the molar ratio of unit (II)/unit (III) ranges from 5/95 to 90/10. A hydrolyzed product of the copolymer or a water-soluble maleic acid copolymer is also provided. The hydrolyzed product is advantageously used for scale inhibitors, dispersants for calcium carbonate or admixtures for cement and conctrete.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.