Abstract: This invention provides a product safe for treating, improving or preventing an inflammatory bowel disease such as ulcerative colitis, and provides a product comprising an insoluble dietary fiber obtained by enzymatic treatment of seeds of a grain plant(s) or germinated young seeds thereof, as well as a food or drink or medicament comprising the product.

Abstract: This invention provides a product safe for treating, improving or preventing an inflammatory bowel disease such as ulcerative colitis, and provides a product comprising an insoluble dietary fiber obtained by enzymatic treatment of seeds of a grain plant(s) or germinated young seeds thereof, as well as a food or drink or medicament comprising the product.

Abstract: A fault test apparatus for testing a fault on each signal line in a circuit under test including signal lines includes a controller, which calculates a value of a fault excitation function for a fault signal line, using the fault excitation function representing a fitness result of a predetermined fault excitation condition between the fault signal line having a fault among the signal lines under test in the circuit under test and at least one of adjacent signal lines adjacent to the fault signal line and falling within a predetermined range from the fault signal line, based on layout information between the fault signal line and at least one adjacent signal line adjacent to the fault signal line, manufacturing parameter information, and timing information, and then, determines whether or not a dynamic fault is excited on the fault signal line based on the value of the fault excitation function.

Abstract: A fault test apparatus for testing a fault on each signal line in a circuit under test including signal lines includes a controller, which calculates a value of a fault excitation function for a fault signal line, using the fault excitation function representing a fitness result of a predetermined fault excitation condition between the fault signal line having a fault among the signal lines under test in the circuit under test and at least one of adjacent signal lines adjacent to the fault signal line and falling within a predetermined range from the fault signal line, based on layout information between the fault signal line and at least one adjacent signal line adjacent to the fault signal line, manufacturing parameter information, and timing information, and then, determines whether or not a dynamic fault is excited on the fault signal line based on the value of the fault excitation function.

Abstract: A first input transistor of a current mirror, in which one end is connected to a first constant current source and another end is connected to a reference potential (for example, the ground), serves as a current mirror input. A second input transistor, in which one end is connected to a second constant current source, is disposed with being separated from the first input transistor by a predetermined distance. A plurality of output transistors is distributed between the first and second input transistors. The gate-source voltages of the output transistors are substantially equal to those of the first and second input transistors. Therefore, it is possible to provide to a current mirror circuit which has a large number of output transistors, an influence due to the wiring resistance of a feeder line are remarkably reduced without increasing the wiring area for forming the feeder line.

Abstract: A first input transistor of a current mirror, in which one end is connected to a first constant current source and another end is connected to a reference potential (for example, the ground), serves as a current mirror input. A second input transistor, in which one end is connected to a second constant current source, is disposed with being separated from the first input transistor by a predetermined distance. A plurality of output transistors is distributed between the first and second input transistors. The gate-source voltages of the output transistors are substantially equal to those of the first and second input transistors. Therefore, it is possible to provide to a current mirror circuit which has a large number of output transistors, an influence due to the wiring resistance of a feeder line are remarkably reduced without increasing the wiring area for forming the feeder line.

Abstract: The present invention includes a light receiving unit having a first and second light receiving element which receive light emitted from a light emitting element via slits formed at a rotary disk and respectively generate detection signals whose phases differ from each other substantially by 90.degree.. A first waveform shaping circuit compares the detection signal from the first light receiving element with a reference value and generates a first detection output of a rectangular waveform. A second waveform shaping circuit compares the detection signal from the second light receiving element with the reference value and generates a second detection output of a rectangular waveform. A peak hold circuit receives the detection signal from the first light receiving element and holds the peak value thereof. A reference value generating circuit generates the reference value depending on the peak value held at the peak hold circuit.

Abstract: A microcomputer features the provision of wiring connected to a program counter, the wiring being used for setting a bit at a particular digit position of the program counter to a logical value "0" in proportion to the storage capacity of a memory actually packaged, and when an instruction for gaining access to the rearmost storage area of the largest memory that can be packaged is executed, an address space to be accessed then is forced to be converted to the rearmost address space on the memory thus packaged on the program counter by means of the wiring, whereby data in the rearmost storage area of the memory actually packaged may be accessed with the same program. A process of producing the microcomputer comprises at least the step of setting data in a memory simultaneously with the provision of the wiring for the program counter.

Abstract: A microcomputer that comprises a standby signal generating circuit for supplying a standby signal to a processor and an initial reset circuit for supplying an initial reset signal to the processor when supply voltage becomes lower than a predetermined value, wherein the standby signal is produced in either case where a standby condition is sustained or imposed to switch the processor from an operation mode to a standby mode so that the supply voltage may be lowered during the standby mode, is characterized by the provision of a blocking circuit for blocking the entrance of the initial reset signal into the processor according to the standby signal thus produced.