Patents by Inventor Hideo Oishi
Hideo Oishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7355266Abstract: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no breakdown occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.Type: GrantFiled: December 4, 2006Date of Patent: April 8, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hideo Oishi
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Publication number: 20070077667Abstract: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no breakdown occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.Type: ApplicationFiled: December 4, 2006Publication date: April 5, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Hideo Oishi
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Patent number: 7151003Abstract: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no break-down occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.Type: GrantFiled: June 25, 2003Date of Patent: December 19, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hideo Oishi
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Publication number: 20050099854Abstract: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no break-down occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.Type: ApplicationFiled: June 25, 2003Publication date: May 12, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Hideo Oishi
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Patent number: 6812766Abstract: The input/output circuit of the present invention includes a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit, driven with a control signal, draws a charge from an n-well diffusion region of the p-channel transistor during output. By the charge drawing, the potential at the n-well diffusion region of the p-channel transistor is kept at the supply voltage during output, and thus the input/output circuit is prevented from deterioration in current flow capability due to a back bias effect.Type: GrantFiled: May 22, 2002Date of Patent: November 2, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideo Oishi, Tadayoshi Seike, Masanori Hirofuji
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Publication number: 20040207457Abstract: The input/output circuit of the present invention includes a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit, driven with a control signal, draws a charge from an n-well diffusion region of the p-channel transistor during output. By the charge drawing, the potential at the n-well diffusion region of the p-channel transistor is kept at the supply voltage during output, and thus the input/output circuit is prevented from deterioration in current flow capability due to a back bias effect.Type: ApplicationFiled: May 14, 2004Publication date: October 21, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hideo Oishi, Tadayoshi Seike, Masanori Hirofuji
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Patent number: 6603316Abstract: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no breakdown occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.Type: GrantFiled: July 17, 2001Date of Patent: August 5, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hideo Oishi
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Publication number: 20020175734Abstract: The input/output circuit of the present invention includes a first p-channel transistor and a charge drawing circuit. The first p-channel transistor is connected to an input/output pad of the semiconductor integrated circuit. The charge drawing circuit, driven with a control signal, draws a charge from an n-well diffusion region of the p-channel transistor during output. By the charge drawing, the potential at the n-well diffusion region of the p-channel transistor is kept at the supply voltage during output, and thus the input/output circuit is prevented from deterioration in current flow capability due to a back bias effect.Type: ApplicationFiled: May 22, 2002Publication date: November 28, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hideo Oishi, Tadayoshi Seike, Masanori Hirofuji
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Publication number: 20020005723Abstract: A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no breakdown occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.Type: ApplicationFiled: July 17, 2001Publication date: January 17, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTDInventor: Hideo Oishi
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Patent number: 4914411Abstract: The electro-magnet relay of the present invention utilizes an iron core and an armature both formed as flat plates stacked together. Further, a stationary leaf spring and a moveable leaf spring are provided in the middle section of the iron core having two legs and being shaped as an inverted U. The armature is supported in a hole located in the insulating substrate and may swing to a degree determined by a striking piece formed on the armature. Coil terminals and contact terminals protruding from the bottom of the insulating substrate are arranged in a single line in the electro-magnetic relay of the present invention and may be installed on a high density printed circuit board.Type: GrantFiled: January 9, 1989Date of Patent: April 3, 1990Assignee: Fuji Electric Co., Ltd.Inventors: Hiroshi Hikita, Katsumi Shibata, Hideo Oishi, Hiroshi Yoshikawa
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Patent number: 4529336Abstract: A method of distributing powdered or granular material to a plurality of feeding ends in a system having a pressurizing tank for pressurizing and fluidizing a powdered or granular material, a plurality of transportation pipes having one ends constituting discharge nozzles opening above a fluidized bed in the tank and the other ends connected to different feeding ends so as to introduce the material to the feeding ends, and a plurality of booster gas supply pipes for supplying respective transportation pipes with a booster gas. The internal pressure of the tank is controlled by a controller provided with a set valve in accordance with the mean value of the terminal pressures at the feeding ends, the mean value of predetermined set flow rates of the booster gas in the booster gas supplying pipes, and the mean value of predetermined set rates of transportation of material to the feeding ends.Type: GrantFiled: April 6, 1983Date of Patent: July 16, 1985Assignees: Kawasaki Steel Corporation, Denka Consultant & Engineering Co., Ltd.Inventors: Yoshinobu Shinozaki, Motozo Yasuno, Tadaaki Iwamura, Hironari Marushima, Yoshiteru Tagawa, Ryoji Takabe, Takashi Moriyama, Shuzo Fujii, Keiichi Achiba, Hideo Oishi, Yasuo Yanagihara, Yoshiaki Masuda
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Patent number: 4214091Abstract: A novel antibiotic No. 2-200 represented by the formula ##STR1## which has a broad antimicrobial spectrum and a process for producing the same by cultivating an antibiotic No. 2-200 producing microorganism of the genus Nocardia, and recovering by isolation the antibiotic No. 2-200 accumulated in the culture.Type: GrantFiled: September 21, 1978Date of Patent: July 22, 1980Assignee: Chugai Seiyaku Kabushiki KaishaInventors: Hideo Oishi, Takao Noto, Yoshiharu Nawata, Hiroshi Okazaki, Hiroshi Sasaki, Kunio Ando, Haruki Ogawa
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Patent number: 4174749Abstract: An air conditioning display system for a vehicle comprising a vehicle's air conditioner proper including a plurality of air intake ducts, a plurality of air discharge ducts, a plurality of dampers, and a fan unit, an air conditioner actuator actuating the dampers and the fan unit thereby introducing and discharging air into and out of the air conditioner proper, and a display device including a display panel carrying the picture of the vehicle body portions around the front seat for displaying the flowing patterns of air out of the air conditioner proper. Illuminating means is disposed behind the display panel and is selectively energized so that the occupant can readily visually confirm the flow air from the duct outlets.Type: GrantFiled: February 27, 1978Date of Patent: November 20, 1979Assignee: Mitsubishi Jidosha Kogyo Kabushiki KaishaInventor: Hideo Oishi