Abstract: An AFC circuit for use in a chrominance signal processing circuit of a VTR basically includes a VCO (9), a frequency divider (9, 10, 11, 12, 13) for frequency-dividing an output of the VCO, and a phase comparing circuit (17) for comparing phases of the output of the divider and a horizontal synchronizing signal extracted from an inputted video signal to supply an error output to the VCO. When a phase relation between the output of the divider and the horizontal synchronizing signal becomes a miss-locked state out of the phase-locked state, a frequency-dividing operation is stopped at a timing corresponding to a rise of a normal inputted signal in a phase-locked state and the frequency-dividing operation is restarted after the inputted horizontal synchronizing signal is counted by a predetermined number. As a result, the phase-locked state of the inputted horizontal synchronizing signal and the output signal of the divider is forcibly restored.