Patents by Inventor Hideo Satou

Hideo Satou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050152731
    Abstract: A guide wire includes a wire body having a first wire disposed at a distal end thereof and a second wire joined to a proximal end of the first wire. The first wire and the second wire are preferably joined to each other by welding, providing a layer joint therebetween. The joint is of a curved shape, particularly a convex curved shape that is convex toward the proximal end of the wire body. In the joint, at least one component (e.g., Ti) of the material of the first wire decreases toward the proximal end and at least one component (e.g., Fe) of the material of the second wire decreases toward the distal end.
    Type: Application
    Filed: December 17, 2004
    Publication date: July 14, 2005
    Applicant: Terumo Kabushiki Kaisha
    Inventors: Katsuro Mishima, Yutaka Itou, Hiraku Murayama, Hideo Satou
  • Patent number: 6850219
    Abstract: A display device is constituted by a display module which determines a plurality of pieces of pixels as belonging to one block unit, selects the plurality of pixels in each block unit at the same time and displays a picture image by adding one or a plurality of specific patterns each having different spatial frequencies of each block unit; a display control unit which controls the display module; a picture image signal generation unit which generates picture image signals; and a computing circuit which generates the specific patterns each having different spatial frequencies while weighting the same based on the picture image signals for every block unit. Thereby, a display device which reduces the signal clock frequency as well as increases the signal writing time, enhances the opening rate of an LC panel and permits a highly fine display and a high speed motion picture display, is obtained.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 1, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Aoyama, Shinichi Komura, Ikuo Hiyama, Tsunenori Yamamoto, Yoshiyuki Kaneko, Mitsuji Ikeda, Osamu Itou, Hideo Satou, Shoichi Hirota
  • Patent number: 6849057
    Abstract: A pressure-sensitive adhesive tape for fixing a joint portion includes a support of a generally rectangular shape having a longer side and a shorter side and a pressure sensitive adhesive layer on one side of the support in at least a portion thereof. The support is provided with a non-adherent portion or a weakly adherent portion. The tape has a cut line extending from an end of the shorter side to near the non-adherent or weakly adherent portion.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: February 1, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Hideo Satou, Masayuki Konno, Kodo Kishida, Yoshitada Morikawa, Osamu Oohira, Seishi Suzuki, Yuichi Inoue
  • Patent number: 6819317
    Abstract: A liquid crystal display wherein display is performed based on the fact that an a.c. voltage is applied to a liquid crystal layer when a switching element establishes a connection between a display electrode and a common electrode, and the a.c. voltage is not applied to the liquid crystal layer when the switching element releases the connection between the display electrode and the common electrode. A state of the switching element changes from connection between the display electrode and the common electrode to release of the connection under a condition that respective voltages of an opposite electrode, the display electrode, and the common electrode are made substantially the same, the condition being produced by stopping an a.c. voltage applied to the opposite electrode.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: November 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Komura, Yoshiro Mikami, Hideo Satou, Minoru Hoshino
  • Patent number: 6784865
    Abstract: By changing circuit connections at predetermined 4 timings, a switch feed through offset cancel circuit which permits canceling fluctuation in output offset of an analog picture image signal voltage due to fluctuation of semiconductor elements characteristics in the circuit. Thereby, a uneven brightness in a form of vertical stripe shape, which deteriorates picture quality, due to fluctuation in switch feed through charges of an offset cancel circuit is eliminated in a TFT LC display device having a buffer amplifier.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: August 31, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hajime Akimoto, Hideo Satou
  • Publication number: 20040135756
    Abstract: In a display matrix in which individual pixels in which a sub scan wiring and a display electrode, a main circuit of TFT controlled by an applied voltage of the main scan wiring and the sub scan wiring, and signal wiring and a display electrode are connected in series are arranged, and the sub scan wiring is arranged in the vertical direction, a line is selected and driven with the main scan pulse shifted sequentially in the individual frame time supplied on the main scan wiring, and with the sub scan pulse varying its state in a time of the main scan pulse.
    Type: Application
    Filed: November 26, 2003
    Publication date: July 15, 2004
    Inventors: Yoshiro Mikami, Hideo Satou, Hiroshi Kageyama, Yoshinori Aono
  • Publication number: 20040135760
    Abstract: A display device has a driver including a level converter formed of polysilicon MISTFTS. The level converter includes first, second and third N-channel MISTFTs (NMISTFTs) and first, second and third P-channel MISTFTs (PMISTFTS). Gate and first terminals of the first NMISTFT and PMISTFT, and a gate terminal of the third PMISTFT are coupled to an input terminal via a capacitance. Second terminals of the second NMISTFT and PMISTFT, and a gate terminal of third NMISTFT are coupled to the input terminal via a capacitance. A first terminal of the third PMISTFT, and second terminals of the first NMISTFT and PMISTFT are coupled to a high voltage. A second terminal of the third NMISTFT, gate and first terminals of the second NMISTFT and PMISTFT are coupled to a low voltage. A second terminal of the third PMISTFT and a first terminal of the third NMISTFT are connected to an output terminal.
    Type: Application
    Filed: December 9, 2003
    Publication date: July 15, 2004
    Inventors: Toshio Miyazawa, Hideo Satou, Tomohiko Satou, Masahiro Maki
  • Patent number: 6727875
    Abstract: In a display matrix in which individual pixels in which a sub scan wiring and a display electrode, a main circuit of TFT controlled by an applied voltage of the main scan wiring and the sub scan wiring, and signal wiring and a display electrode are connected in series are arranged, and the sub scan wiring is arranged in the vertical direction, a line is selected and driven with the main scan pulse shifted sequentially in the individual frame time supplied on the main scan wiring, and with the sub scan pulse varying its state in a time of the main scan pulse.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiro Mikami, Hideo Satou, Hiroshi Kageyama, Yoshinori Aono
  • Patent number: 6686899
    Abstract: A display device has a driver including a level converter formed of polysilicon MISTFTs. The level converter includes first, second and third N-channel MISTFTs (NMISTFTs) and first, second and third P-channel MISTFTs (PMISTFTs). Gate and first terminals of the first NMISTFT and PMISTFT, and a gate terminal of the third PMISTFT are coupled to an input terminal via a capacitance. Second terminals of the second NMISTFT and PMISTFT, and a gate terminal of third NMISTFT are coupled to the input terminal via a capacitance. A first terminal of the third PMISTFT, and second terminals of the first NMISTFT and PMISTFT are coupled to a high voltage. A second terminal of the third NMISTFT, gate and first terminals of the second NMISTFT and PMISTFT are coupled to a low voltage. A second terminal of the third PMISTFT and a first terminal of the third NMISTFT are connected to an output terminal.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: February 3, 2004
    Assignees: Hitachi, Ltd., Hitachi, Device Engineering Co., Ltd.
    Inventors: Toshio Miyazawa, Hideo Satou, Tomohiko Satou, Masahiro Maki
  • Publication number: 20030181828
    Abstract: A guide wire includes a wire body, a first coil, a second coil, and an elongate member. The first coil has a helical shape, and is disposed on a distal end side of the guide wire. The second coil has a helical shape, and is disposed on a distal end side of the first coil. The elongate member has a section that extends a longitudinal direction of the wire body. At least a portion of the section is located inside the second coil, and the elongate member is formed integrally with the first coil or the second coil.
    Type: Application
    Filed: January 28, 2003
    Publication date: September 25, 2003
    Inventors: Katsuharu Fujimoto, Hideo Satou, Shunichi Uchino
  • Publication number: 20030069530
    Abstract: A pressure-sensitive adhesive tape for fixing a joint portion includes a support of a generally rectangular shape having a longer side and a shorter side and a pressure sensitive adhesive layer on one side of the support in at least a portion thereof. The support is provided with a non-adherent portion or a weakly adherent portion. The tape has a cut line extending from an end of the shorter side to near the non-adherent or weakly adherent portion.
    Type: Application
    Filed: May 8, 2002
    Publication date: April 10, 2003
    Applicant: NITTO DENKO CORPORATION
    Inventors: Hideo Satou, Masayuki Konno, Kodo Kishida, Yoshitada Morikawa, Osamu Oohira, Seishi Suzuki, Yuichi Inoue
  • Patent number: 6522317
    Abstract: A liquid-crystal display apparatus includes first and second substrates sandwiching a liquid-crystal, and having a switching element provided at a cross point of a scan line and a data line on the first substrate, a vertical drive circuit for controlling a voltage of the scan line provided on the first substrate, a horizontal drive circuit for controlling a voltage of said data line provided on the first substrate, and a transparent electrode provided on a surface of the second substrate. The horizontal drive circuit includes a reference-voltage generator, a voltage selector, a controller, and a sample-and-hold arrangement.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: February 18, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Satou, Yoshiro Mikami, Hiroshi Kageyama, Takahiro Nagano, Yoshinori Aono, Toshio Miyazawa
  • Publication number: 20020097212
    Abstract: A display device has a driver including a level converter formed of polysilicon MISTFTs. The level converter includes first, second and third N-channel MISTFTs (NMISTFTs) and first, second and third P-channel MISTFTs (PMISTFTs). Gate and first terminals of the first NMISTFT and PMISTFT, and a gate terminal of the third PMISTFT are coupled to an input terminal via a capacitance. Second terminals of the second NMISTFT and PMISTFT, and a gate terminal of third NMISTFT are coupled to the input terminal via a capacitance. A first terminal of the third PMISTFT, and second terminals of the first NMISTFT and PMISTFT are coupled to a high voltage. A second terminal of the third NMISTFT, gate and first terminals of the second NMISTFT and PMISTFT are coupled to a low voltage. A second terminal of the third PMISTFT and a first terminal of the third NMISTFT are connected to an output terminal.
    Type: Application
    Filed: November 19, 2001
    Publication date: July 25, 2002
    Inventors: Toshio Miyazawa, Hideo Satou, Tomohiko Satou, Masahiro Maki
  • Publication number: 20020033786
    Abstract: By changing circuit connections at predetermined 4 timings, a switch feed through offset cancel circuit which permits canceling fluctuation in output offset of an analog picture image signal voltage due to fluctuation of semiconductor elements characteristics in the circuit. Thereby, a uneven brightness in a form of vertical stripe shape, which deteriorates picture quality, due to fluctuation in switch feed through charges of an offset cancel circuit is eliminated in a TFT LC display device having a buffer amplifier.
    Type: Application
    Filed: June 18, 2001
    Publication date: March 21, 2002
    Inventors: Hajime Akimoto, Hideo Satou
  • Publication number: 20020011980
    Abstract: A display device is constituted by a display module which determines a plurality of pieces of pixels as belonging to one block unit, selects the plurality of pixels in each block unit at the same time and displays a picture image by adding one or a plurality of specific patterns each having different spatial frequencies of each block unit; a display control unit which controls the display module; a picture image signal generation unit which generates picture image signals; and a computing circuit which generates the specific patterns each having different spatial frequencies while weighting the same based on the picture image signals for every block unit. Thereby, a display device which reduces the signal clock frequency as well as increases the signal writing time, enhances the opening rate of an LC panel and permits a highly fine display and a high speed motion picture display, is obtained.
    Type: Application
    Filed: May 25, 2001
    Publication date: January 31, 2002
    Inventors: Tetsuya Aoyama, Shinichi Komura, Ikuo Hiyama, Tsunenori Yamamoto, Yoshiyuki Kaneko, Mitsuji Ikeda, Osamu Itou, Hideo Satou, Shoichi Hirota
  • Patent number: 4914261
    Abstract: A cable connecting box for accommodating and protecting the connecting portion of cables in narrow spaces while allowing any branch cables to be led out in a free direction from the cable conecting box. The structural arrangement of the cable connecting box has the following features: (1) an opening is formed at one side wall of a two-split case whereby the longer side edges of the opening are facing each other in the depth-wise direction of the case; (2) a core plate of an elastic material which fits between the casing halves seals the casing water-tight; (3) a plurality of cable receptacles are formed between the core plate and each of the casing halves by combining the semicircular grooves of the core plate with the semicircular grooves which are formed in the longer side edge of the opening in a manner to face the former semicircular grooves.
    Type: Grant
    Filed: September 6, 1988
    Date of Patent: April 3, 1990
    Assignees: Sumitomo Electric Industries, Ltd., Chubu Telecommunications Company Inc.
    Inventors: Yuzo Tokumaru, Hideo Satou, Kunio Kobayashi