Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Abstract: A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink.

Abstract: Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: The throughput of external output actions of read data from memory blocks that are capable of parallel operation is improved.

Abstract: An information processor is capable of eliminating register conflict in short and long latency processes and for attaining high-speed pipeline processing through efficient use of registers. The scale of the necessary hardware is reduced by the processor using a register conflict detector and a scoreboard. The register conflict detector detects register conflict over a period of short latency processing, and the scoreboard checks for register conflict beyond the short latency process period and into a period of long latency processing. The processor controls the issue of instructions based on the detected register conflict status.

Abstract: An information processor having a high performance as a whole is provided by improving the throughput of the processor and the semiconductor memory device. The information processor comprises a memory having a buffer for temporarily holding data and a processor having a memory interface part for controlling the memory to transfer data to the buffer before determining whether the data is to be written in the memory and to write the data in said memory after determining of writing. Data writing and reading to the semiconductor device is pipelined by justifying data exchange between reading and writing. Since the data transfer timings of reading from a memory and writing in the memory can be executed at the same time, the reading process and the writing process can be performed by pipeline-like process and the throughput can be improved.

Abstract: A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Abstract: To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.

Abstract: A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.

Abstract: An information processing apparatus with an address extension function includes a set of address adders for performing address addition with respect to a first fraction of an address for an instruction and/or a data, which fraction corresponds to the not extended bit portion of the address, and a set of domain registers for storing a second fraction of the address for an instruction or an operand, which fraction corresponds to the extended bit portion of the address. If address extension is not made, address translation into a real address is performed using a virtual address obtained through addition operation by the address adder and in accordance with a conventional not address extended program. If address extension is made, address translation into a real address is performed using a virtual address obtained by concatinating the addition result by the address adder with the content of the domain register.

Abstract: A buffer storage control apparatus includes a plurality of sets of buffer address arrays, each of the sets storing the same content and being allocated to one of a plurality of rows of a translation look-aside buffer. With this arrangement, it is possible to reduce the length of wiring lines leading from the translation look-aside buffer to the buffer address arrays and to minimize intersections of the wiring lines, thereby reducing signal delays.