Patents by Inventor Hideo Shitaya

Hideo Shitaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160357470
    Abstract: A method includes: allocating a first divided region in a user space to a program executed in a user mode, the first divided region being one of a plurality of divided regions obtained by dividing a storing region of a memory, storing information which indicates that the data to be stored is confidential, in association with the first divided region allocated to the program; storing, when data stored in the first divided region is copied to a second divided region in a kernel space among the plurality of divided regions of the storing region and when the information is associated with the first divided region, the information in association with the second divided region; and dumping, when the second divided region with which the information is associated is included in a dump target, encryption data which is obtained by encrypting the data stored in the second divided region.
    Type: Application
    Filed: May 27, 2016
    Publication date: December 8, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Naotaka Hamaguchi, Yasuo Ueda, Toshiyuki Okajima, Nobuyuki Akiyama, Hidetoshi Seto, Hideo Shitaya, Hiroyuki Kamezawa
  • Patent number: 9507724
    Abstract: A memory access processing method includes storing, in a cache memory, a plurality of pages stored in a main memory; storing the plurality of pages in a buffer memory, each of the plurality of pages being associated with an identifier indicating whether the each of the plurality of pages being a zero page to be zero-cleared; allocating a page to be set to a zero page, when a page fault occurs during execution of an access to the cache memory and execution of a process is stopped; updating an identifier corresponding to the allocated page to an identifier indicating the allocated page being the zero page; resuming the execution of the process; controlling an access to the cache memory, based on the identifier for each of the plurality of pages; and executing initialization of a page corresponding to the allocated page and is included in the main memory.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiroyuki Kamezawa, Yasuo Ueda, Tsutomu Itoh, Hideo Shitaya, Yasunori Goto, Miyako Uchida, Ken Ichikawa, Hidetoshi Seto
  • Publication number: 20160062902
    Abstract: A memory access processing method includes storing, in a cache memory, a plurality of pages stored in a main memory; storing the plurality of pages in a buffer memory, each of the plurality of pages being associated with an identifier indicating whether the each of the plurality of pages being a zero page to be zero-cleared; allocating a page to be set to a zero page, when a page fault occurs during execution of an access to the cache memory and execution of a process is stopped; updating an identifier corresponding to the allocated page to an identifier indicating the allocated page being the zero page; resuming the execution of the process; controlling an access to the cache memory, based on the identifier for each of the plurality of pages; and executing initialization of a page corresponding to the allocated page and is included in the main memory.
    Type: Application
    Filed: August 3, 2015
    Publication date: March 3, 2016
    Inventors: Hiroyuki KAMEZAWA, Yasuo UEDA, TSUTOMU ITOH, Hideo Shitaya, Yasunori Goto, Miyako Uchida, Ken Ichikawa, Hidetoshi Seto