Patents by Inventor Hideo Sunaga

Hideo Sunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7999444
    Abstract: Power generation technology using tidal power or wave power is provided, especially as related to power generation technology using a piezoelectric element. Power generation technology includes a power generation device for effectively generating electric power in water or on a ship with the use of tidal power or wave force and having power generation modules (5a, 5b) having a piezoelectric element (14) put between plates (1a, 1b, 1c). The plates are placed between two flanges (9b, 10) fixed to a rod (3) penetrating the plates. When the rod (3) inclines due to a water flow, the piezoelectric element (14) is compressed by the two flanges (9b, 10) which generates electric power. Moreover, when the rod (3) is restored from due to reduction of the water flow, thickness of the piezoelectric element (14) is restored which also generates electric power.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: August 16, 2011
    Inventor: Hideo Sunaga
  • Publication number: 20100109482
    Abstract: The present invention relates to a power generation technology using tidal power or wave power, especially relates to a power generation technology using a piezoelectric element. It is an object of the present invention to provide a power generation device for generating electric power in water or on a ship effectively with the use of tidal power or wave force. The present invention has such a structure that power generation modules (5a, 5b) having a piezoelectric element (14) are put between plates (1a, 1b, 1c) and the plates are placed between two flanges (9b, 10) fixed to a rod (3) penetrating the plates. When the rod (3) inclines due to a water flow, the piezoelectric element (14) is compressed by the two flanges (9b, 10) and thereby it generating the electric power. Moreover, when the rod (3) is restored from due to reduction of the water flow, thickness of the piezoelectric element (14) is restored and thereby it generating the electric power.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 6, 2010
    Inventor: Hideo Sunaga
  • Patent number: 7546496
    Abstract: A packet transmission device that is connected to a plurality of communication lines, and transmits a packet received, includes a failure detecting unit that monitors a condition of the communication lines, and detects a failure in the communication lines; and a packet transmitting unit that transmits, when the failure detecting unit detects a failure in a communication line, and when a packet having a same transmission-destination address as an address corresponding to a port of the communication line in which the failure has been detected is received, the packet from all preset ports.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: June 9, 2009
    Assignee: Fujitsu Limited
    Inventors: Toshinori Koyanagi, Hideo Sunaga, Satoshi Nemoto, Shigetoshi Nakai
  • Publication number: 20060107188
    Abstract: A packet transmission device that is connected to a plurality of communication lines, and transmits a packet received, includes a failure detecting unit that monitors a condition of the communication lines, and detects a failure in the communication lines; and a packet transmitting unit that transmits, when the failure detecting unit detects a failure in a communication line, and when a packet having a same transmission-destination address as an address corresponding to a port of the communication line in which the failure has been detected is received, the packet from all preset ports.
    Type: Application
    Filed: February 25, 2005
    Publication date: May 18, 2006
    Inventors: Toshinori Koyanagi, Hideo Sunaga, Satoshi Nemoto, Shigetoshi Nakai
  • Patent number: 6400785
    Abstract: An apparatus for resynchronizing data signals by using dual port data buffer storage, which prevents data corruption and subsequent system disruption from happening by employing a mechanism to keep an adequate distance between read and write address pointers. An input unit receives an incoming data stream having a cyclic data structure of N bytes. A data writing unit sequentially writes each data word of the received data stream into a storage unit with a capacity of 2N bytes in synchronization with a first clock. A data reading unit sequentially reads out each data word from the storage unit in synchronization with a second clock. A detection unit tests whether the write and read address pointers have come within a predetermined threshold distance. A relocation unit moves the read address pointer by N bytes to increase the distance between the read and write address pointers, when the detection unit has detected that the write and read address pointers have come within the threshold distance.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Hideo Sunaga, Nobuyuki Nemoto
  • Patent number: 6252502
    Abstract: An alarm detection apparatus includes a plurality of alarm detectors detecting and/or cancelling alarms for identical and different error rates. The plurality of alarm detectors are grouped into a major detector unit made up of alarm detectors which detect major error rates, and a minor detector unit made up of alarm detectors which detect minor error rates. The major detector unit and the minor detector unit output detection outputs corresponding to specified detection rates thereof. A predetermined alarm detector corresponding to a part of the minor detector unit has a specified detection rate overlapping a specified detection rate of the major detector unit being controlled, so that a detection function or a detection output of the predetermined alarm detector is disabled.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: June 26, 2001
    Assignee: Fujitsu Limited
    Inventors: Masaki Kubo, Masaru Kameda, Shigeyuki Kobayashi, Junichi Ishiwatari, Shuniti Nakayama, Hideo Sunaga, Nobuyuki Nemoto
  • Patent number: 6034947
    Abstract: Provided is a cross connection system for time-division multiplexed signals, upon detection of deterioration in quality, performs line setting to easily switch to a line having another directional orientation.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: March 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Yoshida, Hideo Sunaga, Masashi Tanaka
  • Patent number: 5918501
    Abstract: The invention provides a tool and method for repairing a sheet metal according which a dented portion of a sheet metal can be easily and appropriately pulled out with a minimal force. The tool has a simple structure and adapted to be used in the method. The tool includes an end of an operation shaft 1 having a given length serves as a handle portion 2, and an arc electrode 3 is affixed to the other end. A support stand 4 is attached to an end of the operational shaft 1. The support stand 4 may include a base 5 through which the operational shaft 1 is inserted and affixed thereto, a leg portion 6 extended from the base 5, and a seat portion 7 attached to the lower end of the leg portion 6. With the configuration as above, the arc electrode 3 is welded to a dented portion r of a sheet metal while the seat portion 7 is in contact with the sheet metal surface R, and the operation shaft 1 is tilted in that state, while the seat portion 7 is pressed against the sheet metal surface R.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: July 6, 1999
    Assignee: Kabushiki Kaisha
    Inventors: Hideo Sunaga, Yoshitake Fukushima
  • Patent number: 5247294
    Abstract: A signal select control circuit for a select circuit, which selects one of a plurality of predetermined signals, in accordance with a select signal comprising an arrangement change circuit, a priority-based select circuit, and an arrangement reverse circuit. The arrangement change circuit receives n input signals (n is an integer) arranged in parallel in accordance with a first arrangement and changes an arrangement of the n input signals in accordance with a control signal indicative of a priority order so that the n input signals are arranged in parallel in accordance with a second arrangement based on the priority order. The priority-based select circuit receives the n input signals having the second arrangement and generates n output signals arranged in parallel in accordance with a third fixed arrangement. The n output signals indicates one of the n input signals, which has a highest priority among valid input signals among the n input signals.
    Type: Grant
    Filed: June 14, 1991
    Date of Patent: September 21, 1993
    Assignee: Fujitsu Limited
    Inventor: Hideo Sunaga