Abstract: An organic hydride production device comprises an electrolyzer and a water removal device. The electrolyzer has a cathode chamber. The water removal device has a container that stores a catholyte fed from the cathode chamber, a drain pipe that discharges dragged water from the container, a detector that detects that the dragged water has been accumulated in the container, and a switcher that is provided in the drain pipe, is capable of switching between a regulation state in which drainage from the drain pipe is regulated and an execution state in which the drainage is executed, and switches from the regulation state to the execution state based on a detection result of the detector.

Abstract: A field effect transistor includes an active region provided in a projecting part on a surface of a semiconductor substrate, the projecting part extending in a fixed direction parallel to the surface, and a gate electrode provided on a sidewall of the projecting part along the fixed direction with a gate insulating films interposed.

Abstract: The present invention provides a semiconductor device in which, in order to prevent wiring delay, an electromagnetic wave is radiated from a transmitting dipole antenna placed on a semiconductor chip and received with a receiving antenna placed in a circuit block included in another semiconductor chip, instead of long metal wires or via-hole interconnection.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A semiconductor memory having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor and suppressing expansion of a depletion layer from the groove, and a method for fabricating the same are disclosed. An area occupied by each memory cell can be made very small and a distance between the memory cells can also be made very small, accordingly, high density integration is facilitated.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only-Memory) cannot be configured as a high speed/large capacity memory.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: An apparatus and method for a logic circuit that advantageously adapts to different operating voltages. In a preferred embodiment, a logic circuit of the present invention is implemented to drive a large capacitive load and includes a first driver, comprising a set of small, low-current drive transistors, a second driver, comprising a set of large, high-speed transistors, and an additional transistor connected between the two drivers. The additional transistor can be selectively enabled to speed up the operation of the logic circuit, and disabled to reduce the peak current of the logic circuit. The additional transistor is enabled by a voltage detection signal, which is active when the operating voltage of the chip is at a low level and inactive when the operating voltage of the chip is at a high level.

Abstract: A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.

Abstract: Technology for using a wiring of a superconductive material in semiconductor integrated circuit device. An isolation layer and/or a barrier layer are provided for preventing diffusion of harmful composition of the superconductive material for the semiconductor device. Control of a circuit can be made utilizing the characteristics of a superconductive material. Also, the characteristics of a superconductive material may be controlled. A method of forming a layer of superconductive material, well compatible with the widely used process of manufacturing integrated circuit devices, is also disclosed.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO.sub.2 island is oxidized adjacent its lower end to insulate the island from the substrate.

Abstract: A semiconductor memory is provided having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor. In particular, an arrangement is provided to prevent a depletion region formed around the groove from growing into an adjacent capacitor. By virtue of this, both the area occupied by each memory cell and the distance between the memory cells can be made very small. Accordingly, high density integration is facilitated.