Abstract: A semiconductor integrated circuit includes a substrate which has a predetermined width in a first direction and a predetermined length in a second direction which is approximately perpendicular to the first direction, a plurality of cells which are provided on the substrate and are grouped into a plurality of generally rectangular unit blocks, where each of the unit blocks are made up of cells having mutually different widths in the first direction but a common length in the second direction, first interconnections for supplying at least one power source voltage to the cells, where the first interconnections are provided independently for each unit block so as to supply the power source voltage in common to each of the cells making up the unit block, a row of first terminals of the cells, within each unit block, arranged in the first direction, a row of second terminals of the cells, within each unit block, arranged in the first direction an interconnection region at least including a region which is defined

Abstract: A testing method tests functions of a semiconductor integrated circuit which has a plurality of blocks each having a main block circuit part and an output part. The testing method comprises the steps of supplying a control signal to the output part of each of the blocks in a normal mode so that each output part outputs an output data of the main block circuit part of a corresponding one of the blocks, supplying the control signal and a test data to the output part of each of the blocks in a test mode so that each output part outputs the test data which is supplied to the main block circuit part of another block, and comparing the output data and the test data in the output part of each of the blocks in the test mode and outputting a failure detection signal which is indicative of a failure in a corresponding one of the blocks when the compared output data and test data do not match in the one block.

Abstract: A semiconductor integrated circuit comprises a plurality of first hierarchical units of logic devices each including a plurality of bipolar logic devices having a polycell structure. The bipolar logic devices have a first standardized size in a first direction and are arranged in a second direction for a second standardized size in each first hierarchical unit. Each of the first hierarchical units is defined by first and second main edges extending in the second direction for the second standardized size, and first and second side edges extending in the first direction for the first standardized size. Each of the first hierarchical units consumes a generally identical electric power and has a first power feed system extending in the second direction for the second standardized size for feeding the electric power to the bipolar logic devices therein.

Abstract: A connecting structure for connecting conductors used for wiring in a semiconductor device comprises a first conductor provided on a part of the semiconductor device for passing the flow of electrons, an insulator provided on the first conductor and formed with a contact hole, and a second conductor provided on the insulator for passing the flow of electrons, in which the second conductor is provided so as to sandwich the insulator together with a part of the first conductor. The first and second conductors are contacted to each other across the insulator at the contact hole so that the electrons flow through the contact hole. The contact hole extends in a general direction of a flow of electrons passing therethrough and has a stepped shape in which a width measured perpendicularly to the general direction of the flow of electrons increases stepwise towards the general direction of the flow of electrons.