Patents by Inventor Hideo Tsunemitsu

Hideo Tsunemitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4244002
    Abstract: A semiconductor structure in which metallic connecting leads are bonded to bump terminal electrodes by thermal pressure bonding. A stress mitigation layer is advantageously provided in the semiconductor structure which prevents or reduces breaking of the semiconductor substrate or an insulating film when thermal pressure bonding is applied to the bump terminal electrode.
    Type: Grant
    Filed: October 18, 1978
    Date of Patent: January 6, 1981
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Susumu Sato, Hideo Tsunemitsu
  • Patent number: 4051508
    Abstract: A terminal electrode for a semiconductor device includes a bump terminal comprising first, second, and third metal layers producing a step-like profile. The bump terminal is characterized by improved mechanical strength for gang bonding.
    Type: Grant
    Filed: June 9, 1976
    Date of Patent: September 27, 1977
    Assignee: Nippon Electric Company, Ltd.
    Inventors: Susumu Sato, Hideo Tsunemitsu
  • Patent number: 4001871
    Abstract: An integrated circuit device with multi-level interconnection wiring structure built upon the substrate wherein each level is formed of conductor and insulator portions and wherein each level has a surface substantially parallel to the surface of the substrate.
    Type: Grant
    Filed: October 16, 1974
    Date of Patent: January 4, 1977
    Assignee: Nippon Electric Company, Ltd.
    Inventor: Hideo Tsunemitsu
  • Patent number: 3988214
    Abstract: An integrated circuit device with multi-level interconnection wiring structure built upon the substrate wherein each level is formed of conductor and insulator portions and wherein each level has a surface substantially parallel to the surface of the substrate.The method of fabricating the above-described device wherein a suitable substance such as aluminum is deposited over the surface of the substrate to form a metal film, and wherein the aluminum or other substance is then selectively anodized into insulating portions around conducting channels.
    Type: Grant
    Filed: June 13, 1969
    Date of Patent: October 26, 1976
    Assignee: Nippon Electric Company, Ltd.
    Inventor: Hideo Tsunemitsu
  • Patent number: 3939047
    Abstract: A thermally stable semiconductor device is disclosed in which a thin aluminum film is formed over a silicon oxide film selectively formed on the silicon substrate. A layer of a metal such as tantalum, tungsten, or molybdenum that does not enter into an alloy reaction with silicon at heat treatment temperatures is formed over the thin aluminum film and is covered with a thick aluminum film. Oxides of the upper thick aluminum layer as well as oxides of the non-alloying metal and the lower aluminum layer are selectively formed in alignment with one another at locations where the electrodes are not formed.
    Type: Grant
    Filed: August 29, 1974
    Date of Patent: February 17, 1976
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Hideo Tsunemitsu, Hiroshi Shiba