Abstract: An exhaust pipe through which an exhaust port of an internal combustion engine and a catalyst for purifying an exhaust gas of the internal combustion engine are connected to each other includes a porous portion that is provided on at least a part of an inner peripheral face of the exhaust pipe. A thermal conductivity that the porous portion exhibits in a high temperature state where a temperature of the exhaust gas is as high as it is required to radiate a heat of the exhaust gas through the exhaust pipe is at least ten times higher than a thermal conductivity that the porous portion exhibits in a low temperature state where the temperature of the exhaust gas is as low as it is required to warm the catalyst up.

Abstract: A plurality of membrane elements 14 communicate with a water collecting pipe 16 for collecting permeate from the membrane elements 14, and the pipe channel of the water collecting pipe 16 constitutes an upward-inclined channel at least in the upper region of the pipe channel or a channel increased in height in stages at least in the upper region.

Abstract: A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.

Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Abstract: A processor for processing data and correcting an error occurring in the data, the processor includes: a register that stores data with error check data and error correction data; an error detector that detects an error in the data stored in the register by using the error check data; and an error corrector that corrects the detected error by using the error correction data and that stores the corrected data back into the register.

Abstract: A debugging mechanism equipped within a processor and receiving, as inputs, respective pieces of arithmetic operation data related to a plurality of arithmetic units comprised within the processor, and receiving, as inputs, respective control signals used for the respective arithmetic operations, comprising: an unit which comprises a counter performing a counting operation synchronously with the arithmetic operation and comprises a plurality of OR circuits each receiving, as inputs, any of the respective control signals and a signal that is output when the counter value of the counter is a specific counter value; and a debug storage unit which comprises a plurality of storage units each receiving any of the respective pieces of arithmetic operation data, any of the respective outputs of the individual OR circuits, and the counter value, and each storing the arithmetic operation data and counter value when the output of the input OR circuit is valid.

Abstract: A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit.

Abstract: A method and an apparatus for averaging includes generating a carry using a least significant bit of each of two binary numbers, wherein the two binary numbers include a first binary number and a second binary number, and adding a first shifted binary number, a second shifted binary number, and the carry generated, thereby outputting an average of the two binary numbers. The carry generated is added to the least significant bit position. The first shifted binary number is obtained by right-shifting the first binary number by one bit, and the second shifted binary number by right-shifting the second binary number by one bit.

Abstract: To verify an addition-function of a floating-point adder-subtractor in a processor, parameters such as the number of verification patterns of a verification program are set, a floating-point addition instruction to be verified is created, and operands used for this addition are created at random. The floating-point addition instruction thus created is emulated only by a fixed-point instruction and processed only by using the fixed-point execution element, thereby creating an expectation value. The floating-point addition instruction is computed by using the floating-point adder-subtractor to be verified, and the created expectation value is compared with the operation result. If they do not correspond to each other, the set number of operation patterns is checked. If the number has reached a prescribed value, the operation verification is terminated in the normal manner.

Abstract: The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.

Abstract: The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.

Abstract: In the structure of register files composed of a master register file and a working register file, when data is read, the working register file is accessed. When data is written, the both the master register file and the working register file are accessed. In the working register file, data of the current window, and data preceded thereby, and data followed thereby are stored. Thus, even if the SAVE instruction or the RESTORE instruction are successively executed, instructions can be processed out of order. As a result, the efficiency of the process is improved.

Abstract: A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.

Abstract: A method and an apparatus for averaging includes generating a carry using a least significant bit of each of two binary numbers, wherein the two binary numbers include a first binary number and a second binary number, and adding a first shifted binary number, a second shifted binary number, and the carry generated, thereby outputting an average of the two binary numbers. The carry generated is added to the least significant bit position. The first shifted binary number is obtained by right-shifting the first binary number by one bit, and the second shifted binary number by right-shifting the second binary number by one bit.

Abstract: An Internet communication system is disclosed, that comprises a plurality of ISDN (Integrated Services Digital network) lines, an Internet network connected to the ISDN lines using IP (Internet Protocol) as a common protocol, at least one button telephone apparatus connected to the ISDN lines, and at least one telephone unit connected to the button telephone apparatus, wherein the button telephone apparatus has a selecting means for selecting a conventional telephone function or an Internet telephone function, wherein when the selecting means selects the Internet telephone function, the button telephone apparatus converts dial data received from the telephone unit into an IP address, the dial data representing a call destination, converts data of the audio signal received from the telephone unit into IP packets, and transmits the IP packets to the Internet network.

Abstract: In the structure of register files composed of a master register file and a working register file, when data is read, the working register file is accessed. When data is written, the both the master register file and the working register file are accessed. In the working register file, data of the current window, and data preceded thereby, and data followed thereby are stored. Thus, even if the SAVE instruction or the RESTORE instruction are successively executed, instructions can be processed out of order. As a result, the efficiency of the process is improved.

Abstract: An arithmetic processing method and arithmetic processing device each which can reduce the number of logical stages needed to obtain the final arithmetic result, thus executing an arithmetic process such as a floating-point multiplication at high speed to reduce the arithmetic process time. According to the arithmetic processing method and arithmetic processing device, the possibility that an arithmetic exception occurs in the arithmetic result obtained through an arithmetic process is judged in the middle of the arithmetic process of the dedicated arithmetic processing unit. Transmitting an arithmetic end signal to the instruction control unit is inhibited when it is judged that there is a possibility; the arithmetic process with the possibility is executed by means of another arithmetic unit different from the dedicated arithmetic unit. Thereafter the arithmetic end signal regarding the arithmetic process is transmitted to the instruction control unit.

Abstract: In a wire type teleoperational system, a push-pull cable has a push-pull inner cable which is at one end connected to an operative portion, and the other end connected to a coupler. The push-pull cable further has a push-pull outer cable which encases the push-pull inner cable so that one end of the push-pull outer cable is connected to a guide member which movably supports the coupler. A pull cable has a pull inner cable which is at one end connected to a first operative portion, and at the other end connected to the coupler, and the pull cable further has a pull outer cable which encases the pull inner cable so that one end of the pull outer cable is connected to a displacement member which is movably connected to the guide member.

Abstract: On a stator core, there are wound T-connection primary generating windings such that the second and third single-phase windings are respectively arranged at positions electrically orthogonal to the first single-phase winding. The winding number of the first single-phase winding is 31/2 times that of the second single-phase winding or the third single-phase winding. The stator excitation windings are also wound on the stator core, which are connected to the center taps of the primary generating windings through a control rectifier. A plurality of field windings are wound on a rotor core. The field windings are arranged at positions where they are magnetically coupled with both the odd-order spatial higher harmonic components of armature reaction magnetic fields produced by currents flowing in the primary generating windings and the static magnetic fields produced by current flowing in the stator excitation windings.

Abstract: A connecting method comprising laminating a flexible circuit substrate having a plurality of bump contacts with a contact object having a plurality of portions to be contacted such that the respective bump contacts face to the portions to be contacted at a joined surface, correspondingly each other to form a laminate, and applying pressure to the entire surface of the laminate in a compressing direction with pressurizing means provided so as to pinch the laminate in a laminating direction to contact the plural bump contacts mounted on the flexible circuit substrate with the plural portions to be contacted corresponding thereto mounted on the contact object, respectively.