Patents by Inventor Hideomi Kumano

Hideomi Kumano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160064449
    Abstract: A method of manufacturing a junction field effect transistor having a channel region disposed in a semiconductor substrate, deeper than one of a source region and a drain region, the method includes a first step of forming a first mask having a first opening portion over the semiconductor substrate in which a first semiconductor region of a first conductivity type is disposed, a second step of forming a second semiconductor region of a second conductivity type defined as the channel region, in the first semiconductor region by implantation of ions of second conductivity type opposite to the first conductivity type using the first mask, and a third step of forming a third semiconductor region of the second conductivity type defined as the one of the source region and the drain region, by implantation of ions of the second conductivity type, using the first mask.
    Type: Application
    Filed: August 26, 2015
    Publication date: March 3, 2016
    Inventor: Hideomi Kumano
  • Patent number: 9263657
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: February 16, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Publication number: 20150349228
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Application
    Filed: August 11, 2015
    Publication date: December 3, 2015
    Inventor: Hideomi Kumano
  • Patent number: 9136163
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: September 15, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Publication number: 20150179698
    Abstract: A junction type field effect transistor (JFET) in a substrate includes channel and source regions of a first conductivity type and first through fourth gate regions of a second conductivity type. The first and second gate regions are disposed in a direction along a surface of the substrate. The third and fourth gate regions are disposed in the direction. The first and third gate regions are disposed in a depth direction. The first gate region is disposed between the surface and the third gate region. The second and fourth gate regions are disposed in the depth direction. The second gate region is disposed between the surface and the fourth gate region. The channel region includes a first region disposed between the first and third gate regions and a second region disposed between the second and fourth gate regions. The source region is disposed between the first and second gate regions.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 25, 2015
    Inventors: Mahito Shinohara, Hideomi Kumano
  • Patent number: 8980540
    Abstract: A solid-state image sensor is manufactured through a plurality of photolithography processes. The plurality of photolithography processes includes at least one first lithography process including a dividing exposure step of exposing a substrate using a plurality of photomasks, and at least one second lithography process including a non-dividing exposure step of exposing the substrate using one photomask. The at least one first lithography process includes a process for forming a resist pattern to define active regions on the substrate, and a process for forming a resist pattern to define charge accumulation region.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Patent number: 8970769
    Abstract: A solid-state imaging apparatus comprising a substrate having a first face and a second face opposing each other, and in which photoelectric conversion portions are formed, an optical system including microlenses provided on a side of the first face, and light absorbing portions provided on a side of the second face, wherein the apparatus has pixels of first type for detecting light of a first wavelength and second type for detecting light of a second wavelength shorter than the first wavelength, and the apparatus further comprises a first portion between the substrate and the light absorbing portion for each first type pixel, and a second portion between the substrate and the light absorbing portion for each second type pixel, and the first portion has a reflectance higher than that of the second portion for the light of the first wavelength.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: March 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mahito Shinohara, Masatsugu Itahashi, Hideomi Kumano
  • Patent number: 8809094
    Abstract: A method of manufacturing a solid-state image sensor, comprising preparing a semiconductor substrate including a photoelectric converter and an insulating film which includes an opening and is formed in a region above the photoelectric converter, depositing a material having a refractive index higher than the insulating film in the opening, and annealing the material deposited in the opening by irradiating the material with one of light and radiation, wherein a light waveguide which is configured to guide an incident light to the photoelectric converter is formed through the depositing and the annealing.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: August 19, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Publication number: 20140118602
    Abstract: A solid-state imaging apparatus comprising a substrate having a first face and a second face opposing each other, and in which photoelectric conversion portions are formed, an optical system including microlenses provided on a side of the first face, and light absorbing portions provided on a side of the second face, wherein the apparatus has pixels of first type for detecting light of a first wavelength and second type for detecting light of a second wavelength shorter than the first wavelength, and the apparatus further comprises a first portion between the substrate and the light absorbing portion for each first type pixel, and a second portion between the substrate and the light absorbing portion for each second type pixel, and the first portion has a reflectance higher than that of the second portion for the light of the first wavelength.
    Type: Application
    Filed: October 4, 2013
    Publication date: May 1, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Mahito Shinohara, Masatsugu Itahashi, Hideomi Kumano
  • Publication number: 20140111664
    Abstract: A back-side illumination image capturing apparatus includes a semiconductor substrate having a first surface for receiving incident light and a second surface located on the opposite side as the first surface, and including a photoelectric conversion portion, and a gate electrode disposed above the second surface. The apparatus further includes a first insulating layer disposed above the second surface of the semiconductor substrate, an interlayer insulation film disposed on the first insulating layer, a contact plug connected to the gate electrode, and a light-cutting portion for cutting light, of the incident light, that has passed through the photoelectric conversion portion. The light-cutting portion passes through at least part of the interlayer insulation film. The first insulating layer is located between the light-cutting portion and the semiconductor substrate.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 24, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hideomi Kumano
  • Publication number: 20130321680
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 5, 2013
    Inventor: Hideomi Kumano
  • Patent number: 8471196
    Abstract: A photoelectric conversion apparatus includes an effective pixel region for outputting a signal according to light, and an optical black pixel region for outputting a reference signal, wherein, in the optical black pixel region, a plug is arranged in an insulating film, and a light shielding film is arranged above the plug and is connected to the plug, such that an upper surface of the plug and an upper surface of the insulating film form the same plane, and wherein, above or below the light shielding film, a titanium film of thickness 5 to 15 nm is arranged.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: June 25, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Publication number: 20120322196
    Abstract: A method of manufacturing a solid-state image sensor, comprising preparing a semiconductor substrate including a photoelectric converter and an insulating film which includes an opening and is formed in a region above the photoelectric converter, depositing a material having a refractive index higher than the insulating film in the opening, and annealing the material deposited in the opening by irradiating the material with one of light and radiation, wherein a light waveguide which is configured to guide an incident light to the photoelectric converter is formed through the depositing and the annealing.
    Type: Application
    Filed: May 22, 2012
    Publication date: December 20, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hideomi Kumano
  • Publication number: 20110084196
    Abstract: A photoelectric conversion apparatus includes an effective pixel region for outputting a signal according to light, and an optical black pixel region for outputting a reference signal, wherein, in the optical black pixel region, a plug is arranged in an insulating film, and a light shielding film is arranged above the plug and is connected to the plug, such that an upper surface of the plug and an upper surface of the insulating film form the same plane, and wherein, above or below the light shielding film, a titanium film of thickness 5 to 15 nm is arranged.
    Type: Application
    Filed: September 29, 2010
    Publication date: April 14, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hideomi Kumano