Patents by Inventor Hideshi Miyajima
Hideshi Miyajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11417626Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a first substrate having a first elastic modulus is joined onto a second substrate having a second elastic modulus higher than the first elastic modulus. A first semiconductor element is formed on the first substrate. The first substrate is detached from the second substrate.Type: GrantFiled: August 31, 2020Date of Patent: August 16, 2022Assignee: Kioxia CorporationInventors: Mie Matsuo, Hideshi Miyajima
-
Publication number: 20210074672Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a first substrate having a first elastic modulus is joined onto a second substrate having a second elastic modulus higher than the first elastic modulus. A first semiconductor element is formed on the first substrate. The first substrate is detached from the second substrate.Type: ApplicationFiled: August 31, 2020Publication date: March 11, 2021Applicant: Kioxia CorporationInventors: Mie MATSUO, Hideshi MIYAJIMA
-
Patent number: 8822342Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.Type: GrantFiled: December 30, 2010Date of Patent: September 2, 2014Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Ravi Prakash Srivastava, Oluwafemi. O. Ogunsola, Craig Child, Muhammed Shafi Kurikka Valappil Pallachalil, Habib Hichri, Matthew Angyal, Hideshi Miyajima
-
Publication number: 20140054754Abstract: Systems and methods are presented for filling an opening with material of a high integrity. A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer is utilized. Utilizing the material as a mask layer and subsequently removing the material enables a number of mask layers to be minimized in a subsequent filling operation (e.g., metallization). Material amenable to being in a first physical state and a second physical state is an optically reactive material. The optically reactive dielectric can comprise an element or compound which can act as an agent/catalyst in the optical conversion process along with any element or compound which can act as an accelerator for the optical reaction. Conversion can be brought about by exposure to electromagnetic radiation and/or application of thermal energy.Type: ApplicationFiled: August 21, 2012Publication date: February 27, 2014Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Tadayoshi Watanabe, Hideaki Masuda, Hideshi Miyajima
-
Publication number: 20140027914Abstract: Systems and methods are presented for preventing removal of material comprising a metal gate during removal of a mask layer in a semiconductor structure. Upon exposure of the metal line during formation of a via opening the exposed portion of the metal line undergoes chemical modification to form a passivation layer. The passivation layer is subsequently covered by an etch selectivity layer, wherein the etch selectivity layer prevents removal of at least one of a portion of the metal line or the passivation layer during removal of a hard mask layer comprising the semiconductor structure. In an alternate approach, the metal line is formed with a capping layer which, following exposure by a via opening formed in the semiconductor structure, is chemically modified to form a layer having etch selectivity to acts as a protective layer during removal of a hard mask layer comprising the semiconductor layer.Type: ApplicationFiled: July 24, 2012Publication date: January 30, 2014Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Hideyuki Tomizawa, Masao Ishikawa, Hideshi Miyajima
-
Publication number: 20130171819Abstract: Described herein are methods for copper/low-k dielectric material integration. The methods involve depositing and curing a low-k dielectric material and depositing a mask on the low-k dielectric material. A via is patterned in the low-k dielectric material and a trench is patterned in the low-k dielectric material. After the via or trench is patterned, a portion of the low-k material is backfilled with a backfill material. The trench and via are filled with copper, then the mask and the copper filling the via are removed. After a first pre-CLN, the backfill material is removed. This creates a robust copper/porous low-k dielectric material interconnect.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Hideshi Miyajima, Hideaki Masuda
-
Publication number: 20120168957Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., ADVANCED MICRO DEVICES CORPORATIONInventors: Ravi Prakash SRIVASTAVA, Oluwafemi O. OGUNSOLA, Craig CHILD, Muhammed Shafi Kurikka Valappil PALLACHALIL, Habib HICHRI, Matthew ANGYAL, Hideshi MIYAJIMA
-
Publication number: 20120139033Abstract: Semiconductors devices and methods of making semiconductor devices are provided. According to one embodiment, a semiconductor device can include a p-type field effect transistor area having an active region with an epitaxial layer grown thereupon and an isolation feature adjacent to the active region. A height of the isolation feature equals or exceeds a height of an interface between the epitaxial layer and the active region. More particularly, a height of the isolation feature in the corner of a junction between the isolation feature and the action region equals or exceeds the height to the interface between the epitaxial layer and the active region.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Hiroyuki Yamasaki, Hideshi Miyajima, Yoshihiro Uozumi
-
Patent number: 8008190Abstract: Disclosed is a method of manufacturing a semiconductor device which includes: providing an insulating film formed above a semiconductor substrate with a processed portion; supplying a surface of the processed portion of the insulating film with a primary reactant from a reaction of a raw material including at least a Si-containing compound; and subjecting the primary reactant to dehydration condensation to form a silicon oxide film on the surface of the processed portion.Type: GrantFiled: June 20, 2008Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhide Yamada, Hideto Matsuyama, Hideshi Miyajima
-
Patent number: 7999356Abstract: According to one aspect of the present invention, there is provided a composition for film formation, comprising a compound represented by general formula (I) or a hydrolyzed-dehydrocondensation product thereof: X13-mR1mSiR2SiR3nX23-n??(I) wherein R1 and R3 represent a hydrogen atom or a monovalent substituent; R2 represents a divalent group having an alicyclic structure with four carbon atoms or a derivative of the divalent group; X1 and X2 represent a hydrolysable group; and m and n are an integer of from 0 to 2.Type: GrantFiled: August 27, 2009Date of Patent: August 16, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Nakasaki, Nobuhide Yamada, Miyoko Shimada, Hideshi Miyajima, Kei Watanabe
-
Patent number: 7855141Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.Type: GrantFiled: July 13, 2009Date of Patent: December 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
-
Patent number: 7842518Abstract: A method for fabricating a semiconductor device, includes forming a porous dielectric film above a substrate using a porous insulating material, forming an opening in the porous dielectric film, repairing film quality of the porous dielectric film on a surface of the opening by feeding a predetermined gas replacing a Si—OH group to the opening, and performing pore sealing of the surface of the opening using the same predetermined gas as that used for film quality repairs after repairing the film quality.Type: GrantFiled: November 1, 2007Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Hideshi Miyajima
-
Patent number: 7795142Abstract: A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material.Type: GrantFiled: February 12, 2009Date of Patent: September 14, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Masuda, Hideshi Miyajima, Toshiaki Idaka
-
Patent number: 7745326Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.Type: GrantFiled: July 13, 2009Date of Patent: June 29, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
-
Publication number: 20100072581Abstract: According to one aspect of the present invention, there is provided a composition for film formation, comprising a compound represented by general formula (I) or a hydrolyzed-dehydrocondensation product thereof: X13-mR1mSiR2SiR3nX23-n??(I) wherein R1 and R3 represent a hydrogen atom or a monovalent substituent; R2 represents a divalent group having an alicyclic structure with four carbon atoms or a derivative of the divalent group; X1 and X2 represent a hydrolysable group; and m and n are an integer of from 0 to 2.Type: ApplicationFiled: August 27, 2009Publication date: March 25, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasushi Nakasaki, Nobuhide Yamada, Miyoko Shimada, Hideshi Miyajima, Kei Watanabe
-
Publication number: 20090275194Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.Type: ApplicationFiled: July 13, 2009Publication date: November 5, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
-
Patent number: 7589014Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.Type: GrantFiled: November 30, 2006Date of Patent: September 15, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
-
Publication number: 20090203201Abstract: A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material.Type: ApplicationFiled: February 12, 2009Publication date: August 13, 2009Inventors: Hideaki MASUDA, Hideshi MIYAJIMA, Toshiaki IDAKA
-
Patent number: 7569498Abstract: A manufacturing method of a semiconductor device, includes forming a porous organo-siloxane film containing a porogen component having carbon as a main component above a semiconductor substrate, forming an upper-side insulating film having at least one of film density and film composition different from that of the porous organo-siloxane film on the porous organo-siloxane film, and applying at least one of an electron beam and an ultraviolet ray to the porous organo-siloxane film and upper-side insulating film to cause polymerization reaction of the porogen component in the porous organo-siloxane film.Type: GrantFiled: January 25, 2008Date of Patent: August 4, 2009Assignees: Kabushiki Kaisha Toshiba, Sony CorporationInventors: Hideaki Masuda, Hideshi Miyajima, Tsutomu Shimayama
-
Patent number: 7534717Abstract: The formation of an interlayer insulating film above a substrate, the formation of an insulating film of an organic material on the interlayer insulating film thereafter, and the irradiation of the insulating film of an organic material and the interlayer insulating film with electron beams, thereby curing at least the insulating film of an organic material, are proposed.Type: GrantFiled: March 31, 2005Date of Patent: May 19, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hideshi Miyajima, Keiji Fujita, Hideaki Masuda, Rempei Nakata, Miyoko Shimada