Abstract: Performance is improved in a wireless communication terminal in which an antenna is connected to a transmission circuit and a reception circuit. A transmission/reception switching circuit includes a first N-type transistor and a second N-type transistor. The first N-type transistor has a drain connected to the antenna and a gate to which a constant voltage is applied. Furthermore, the second N-type transistor has a drain connected to a source of the first N-type transistor and a gate to which a transmission signal is input. Furthermore, the second N-type transistor supplies a reception signal from one of a source and the drain.

Abstract: LDPC coding is executed using a check matrix of an LDPC code whose code length is 736 bits and whose code rate is 1/4, and modulation is executed using a repetition unit that has an LDPC code obtained by the LDPC coding, repeatedly arranged therein. The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the parity matrix portion has a stepwise structure, the information matrix portion is indicated by a check matrix initial value table, and the check matrix initial value table is a predetermined table indicating positions of elements of “1” of the information matrix portion for each eight columns. This technique is applicable to, for example, information transmission using the LDPC code.

Abstract: LDPC coding is executed using a check matrix of an LDPC code whose code length is 736 bits and whose code rate is 1/4, and modulation is executed using a repetition unit that has an LDPC code obtained by the LDPC coding, repeatedly arranged therein. The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the parity matrix portion has a stepwise structure, the information matrix portion is indicated by a check matrix initial value table, and the check matrix initial value table is a predetermined table indicating positions of elements of “1” of the information matrix portion for each eight columns. This technique is applicable to, for example, information transmission using the LDPC code.

Abstract: A bias circuit according to the present invention includes a monitoring circuit having a second FET and a resistance connected to a drain of the second FET for monitoring a drain current of a first FET to be supplied with a gate bias; a differential circuit including a third FET having a gate supplied with a reference voltage, a fourth FET having a gate connected to the drain of the second FET, sources of the third FET and the fourth FET being connected to a common point, and resistances connected to drains of the third FET and the fourth FET, respectively; and a fifth FET having a drain connected to the common source of the third FET and the fourth FET; wherein a drain voltage of the third FET is fed back to gates of the first FET and the second FET, and a drain voltage of the fourth FET is fed back to a gate of the fifth FET.

Abstract: A bias circuit according to the present invention includes a monitoring circuit having a second FET and a resistance connected to a drain of the second FET for monitoring a drain current of a first FET to be supplied with a gate bias; a differential circuit including a third FET having a gate supplied with a reference voltage, a fourth FET having a gate connected to the drain of the second FET, sources of the third FET and the fourth FET being connected to a common point, and resistances connected to drains of the third FET and the fourth FET, respectively; and a fifth FET having a drain connected to the common source of the third FET and the fourth FET; wherein a drain voltage of the third FET is fed back to gates of the first FET and the second FET, and a drain voltage of the fourth FET is fed back to a gate of the fifth FET.